MPAMIDR_EL1, MPAM ID Register (EL1)
The MPAMIDR_EL1 characteristics are:
Purpose
Indicates the presence and maximum PARTID and PMG values supported in the implementation. It also indicates whether the implementation supports MPAM virtualization.
Configuration
This register is present only when FEAT_MPAM is implemented. Otherwise, direct accesses to MPAMIDR_EL1 are UNDEFINED.
Attributes
MPAMIDR_EL1 is a 64-bit register.
Field descriptions
The MPAMIDR_EL1 bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| RES0 | HAS_SDEFLT | HAS_FORCE_NS | RES0 | HAS_TIDR | RES0 | PMG_MAX | |||||||||||||||||||||||||
| RES0 | VPMR_MAX | HAS_HCR | RES0 | PARTID_MAX | |||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MPAMIDR_EL1 indicates the MPAM implementation parameters of the PE.
Bits [63:62]
Reserved, RES0.
HAS_SDEFLT, bit [61]
HAS_SDEFLT indicates support for MPAM3_EL3.SDEFLT bit. Defined values are:
| HAS_SDEFLT | Meaning |
|---|---|
| 0b0 |
The SDEFLT bit is not implemented in MPAM3_EL3. |
| 0b1 |
The SDEFLT bit is implemented in MPAM3_EL3. |
When MPAM3_EL3.SDEFLT == 1, accesses from the Secure execution state use the default PARTID, PARTID == 0.
HAS_FORCE_NS, bit [60]
HAS_FORCE_NS indicates support for MPAM3_EL3.FORCE_NS bit. Defined values are:
| HAS_FORCE_NS | Meaning |
|---|---|
| 0b0 |
The FORCE_NS bit is not implemented in MPAM3_EL3. |
| 0b1 |
The FORCE_NS bit is implemented in MPAM3_EL3. |
When MPAM3_EL3.FORCE_NS == 1, accesses from the Secure execution state have MPAM_NS == 1.
Bit [59]
Reserved, RES0.
HAS_TIDR, bit [58]
HAS_TIDR indicates support for MPAM2_EL2.TIDR bit. Defined values are:
| HAS_TIDR | Meaning |
|---|---|
| 0b0 |
The TIDR bit is not implemented in MPAM2_EL2. |
| 0b1 |
The TIDR bit is implemented in MPAM2_EL2. |
Bits [57:40]
Reserved, RES0.
PMG_MAX, bits [39:32]
The largest value of PMG that the implementation can generate. The PMG_I and PMG_D fields of every MPAMn_ELx must implement at least enough bits to represent PMG_MAX.
Bits [31:21]
Reserved, RES0.
VPMR_MAX, bits [20:18]
When MPAMIDR_EL1.HAS_HCR == 1:
When MPAMIDR_EL1.HAS_HCR == 1:
Indicates the maximum register index n for the MPAMVPM<n>_EL2 registers.
Otherwise:
Otherwise:
Reserved, RAZ.
HAS_HCR, bit [17]
HAS_HCR indicates that the PE implementation supports MPAM virtualization, including MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM<n>_EL2 with n in the range 0 to VPMR_MAX. Must be 0 if EL2 is not implemented in either security state.
| HAS_HCR | Meaning |
|---|---|
| 0b0 |
MPAM virtualization is not supported. |
| 0b1 |
MPAM virtualization is supported. |
Bit [16]
Reserved, RES0.
PARTID_MAX, bits [15:0]
The largest value of PARTID that the implementation can generate. The PARTID_I and PARTID_D fields of every MPAMn_ELx must implement at least enough bits to represent PARTID_MAX.
Accessing the MPAMIDR_EL1
Accesses to this register use the following encodings:
MRS <Xt>, MPAMIDR_EL1
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b1010 | 0b0100 | 0b100 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
elsif EL2Enabled() && MPAMIDR_EL1.HAS_HCR == '1' && MPAMHCR_EL2.TRAP_MPAMIDR_EL1 == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && MPAMIDR_EL1.HAS_TIDR == '1' && MPAM2_EL2.TIDR == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
return MPAMIDR_EL1;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
return MPAMIDR_EL1;
elsif PSTATE.EL == EL3 then
return MPAMIDR_EL1;