PMMIR_EL1, Performance Monitors Machine Identification Register
The PMMIR_EL1 characteristics are:
Purpose
Describes Performance Monitors parameters specific to the implementation to software.
Configuration
This register is present only when FEAT_PMUv3p4 is implemented. Otherwise, direct accesses to PMMIR_EL1 are UNDEFINED.
Attributes
PMMIR_EL1 is a 64-bit register.
Field descriptions
The PMMIR_EL1 bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | BUS_WIDTH | BUS_SLOTS | SLOTS | ||||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:20]
Reserved, RES0.
BUS_WIDTH, bits [19:16]
From Armv8.7:
From Armv8.7:
Bus width. Indicates the number of bytes each BUS_ACCESS event relates to. Encoded as Log2(number of bytes), plus one. Defined values are:
| BUS_WIDTH | Meaning |
|---|---|
| 0b0000 |
The information is not available. |
| 0b0011 |
Four bytes. |
| 0b0100 |
8 bytes. |
| 0b0101 |
16 bytes. |
| 0b0110 |
32 bytes. |
| 0b0111 |
64 bytes. |
| 0b1000 |
128 bytes. |
| 0b1001 |
256 bytes. |
| 0b1010 |
512 bytes. |
| 0b1011 |
1024 bytes. |
| 0b1100 |
2048 bytes. |
All other values are reserved.
Each transfer is up to this number of bytes. An access might be smaller than the bus width.
When this field is nonzero, each access counted by BUS_ACCESS is at most BUS_WIDTH bytes. An implementation might treat a wide bus as multiple narrower buses, such that a wide access on the bus increments the BUS_ACCESS counter by more than one.
Otherwise:
Otherwise:
Reserved, RAZ.
BUS_SLOTS, bits [15:8]
From Armv8.7:
From Armv8.7:
Bus count. The largest value by which the BUS_ACCESS event might increment by in a single BUS_CYCLES cycle.
If the information is not available, this field will read as zero.
Otherwise:
Otherwise:
Reserved, RAZ.
SLOTS, bits [7:0]
Operation width. The largest value by which the STALL_SLOT event might increment by in a single cycle. If the STALL_SLOT event is not implemented, this field might read as zero.
Accessing the PMMIR_EL1
Accesses to this register use the following encodings:
MRS <Xt>, PMMIR_EL1
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b1001 | 0b1110 | 0b110 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then
UNDEFINED;
elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.PMMIR_EL1 == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && MDCR_EL2.TPM == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
return PMMIR_EL1;
elsif PSTATE.EL == EL2 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then
UNDEFINED;
elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
return PMMIR_EL1;
elsif PSTATE.EL == EL3 then
return PMMIR_EL1;