TRCIDR5, ID Register 5
The TRCIDR5 characteristics are:
Purpose
Returns the tracing capabilities of the trace unit.
Configuration
AArch64 System register TRCIDR5 bits [31:0] are architecturally mapped to External register TRCIDR5[31:0] .
This register is present only when FEAT_ETE is implemented. Otherwise, direct accesses to TRCIDR5 are UNDEFINED.
Attributes
TRCIDR5 is a 64-bit register.
Field descriptions
The TRCIDR5 bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | NUMCNTR | NUMSEQSTATE | RES0 | LPOVERRIDE | ATBTRIG | TRACEIDSIZE | RES0 | NUMEXTINSEL | NUMEXTIN | ||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:31]
Reserved, RES0.
NUMCNTR, bits [30:28]
Indicates the number of Counters that are available for tracing.
| NUMCNTR | Meaning |
|---|---|
| 0b000 |
No Counters are available. |
| 0b001 |
One Counter implemented. |
| 0b010 |
Two Counters implemented. |
| 0b011 |
Three Counters implemented. |
| 0b100 |
Four Counters implemented. |
All other values are reserved.
If TRCIDR4.NUMRSPAIR == 0b0000 then this field is 0b000.
NUMSEQSTATE, bits [27:25]
Indicates if the Sequencer is implemented and the number of Sequencer states that are implemented.
| NUMSEQSTATE | Meaning |
|---|---|
| 0b000 |
The Sequencer is not implemented. |
| 0b100 |
Four Sequencer states are implemented. |
All other values are reserved.
If TRCIDR4.NUMRSPAIR == 0b0000 then this field is 0b000.
Bit [24]
Reserved, RES0.
LPOVERRIDE, bit [23]
Indicates support for Low-power Override Mode.
| LPOVERRIDE | Meaning |
|---|---|
| 0b0 |
The trace unit does not support Low-power Override Mode. |
| 0b1 |
The trace unit supports Low-power Override Mode. |
ATBTRIG, bit [22]
Indicates if the implementation can support ATB triggers.
| ATBTRIG | Meaning |
|---|---|
| 0b0 |
The implementation does not support ATB triggers. |
| 0b1 |
The implementation supports ATB triggers. |
If TRCIDR4.NUMRSPAIR == 0b0000 then this field is 0b0.
TRACEIDSIZE, bits [21:16]
Indicates the trace ID width.
| TRACEIDSIZE | Meaning |
|---|---|
| 0b000000 |
The external trace interface is not implemented. |
| 0b000111 |
The implementation supports a 7-bit trace ID. |
All other values are reserved.
Note that AMBA ATB requires a 7-bit trace ID width.
Bits [15:12]
Reserved, RES0.
NUMEXTINSEL, bits [11:9]
Indicates how many External Input Selector resources are implemented.
| NUMEXTINSEL | Meaning |
|---|---|
| 0b000 |
No External Input Selector resources are available. |
| 0b001 |
1 External Input Selector resource is available. |
| 0b010 |
2 External Input Selector resources are available. |
| 0b011 |
3 External Input Selector resources are available. |
| 0b100 |
4 External Input Selector resources are available. |
All other values are reserved.
NUMEXTIN, bits [8:0]
Indicates how many External Inputs are implemented.
| NUMEXTIN | Meaning |
|---|---|
| 0b111111111 |
Unified PMU event selection. |
All other values are reserved.
Accessing the TRCIDR5
Accesses to this register use the following encodings:
MRS <Xt>, TRCIDR5
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b10 | 0b001 | 0b0000 | 0b1101 | 0b111 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TTA == '1' then
UNDEFINED;
elsif CPACR_EL1.TTA == '1' then
AArch64.SystemAccessTrap(EL1, 0x18);
elsif EL2Enabled() && CPTR_EL2.TTA == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.TRCID == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
return TRCIDR5;
elsif PSTATE.EL == EL2 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TTA == '1' then
UNDEFINED;
elsif CPTR_EL2.TTA == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
return TRCIDR5;
elsif PSTATE.EL == EL3 then
if CPTR_EL3.TTA == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
return TRCIDR5;