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TRCRSCTLR<n>, Resource Selection Control Register <n>, n = 2 - 31

The TRCRSCTLR<n> characteristics are:

Purpose

Controls the selection of the resources in the trace unit.

Configuration

AArch64 System register TRCRSCTLR<n> bits [31:0] are architecturally mapped to External register TRCRSCTLR<n>[31:0] .

This register is present only when FEAT_ETE is implemented and ((AArch64-TRCIDR4.NUMRSPAIR + 1) * 2) > n. Otherwise, direct accesses to TRCRSCTLR<n> are UNDEFINED.

Resource selector 0 always returns FALSE.

Resource selector 1 always returns TRUE.

Resource selectors are implemented in pairs. Each odd numbered resource selector is part of a pair with the even numbered resource selector that is numbered as one less than it. For example, resource selectors 2 and 3 form a pair.

Attributes

TRCRSCTLR<n> is a 64-bit register.

Field descriptions

The TRCRSCTLR<n> bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
RES0PAIRINVINVGROUPSELECT

Bits [63:22]

Reserved, RES0.

PAIRINV, bit [21]

When n is even:

Controls whether the combined result from a resource selector pair is inverted.

PAIRINVMeaning
0b0

Do not invert the combined output of the 2 resource selectors.

0b1

Invert the combined output of the 2 resource selectors.

If:

  • A is the register TRCRSCTLR<n>.
  • B is the register TRCRSCTLR<n+1>.

Then the combined output of the 2 resource selectors A and B depends on the value of (A.PAIRINV, A.INV, B.INV) as follows:

  • 0b000 -> A and B.
  • 0b001 -> Reserved.
  • 0b010 -> not(A) and B.
  • 0b011 -> not(A) and not(B).
  • 0b100 -> not(A) or not(B).
  • 0b101 -> not(A) or B.
  • 0b110 -> Reserved.
  • 0b111 -> A or B.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

INV, bit [20]

Controls whether the resource, that TRCRSCTLR<n>.GROUP and TRCRSCTLR<n>.SELECT selects, is inverted.

INVMeaning
0b0

Do not invert the output of this selector.

0b1

Invert the output of this selector.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

GROUP, bits [19:16]

Selects a group of resources.

GROUPMeaningSELECT
0b0000

External Input Selectors.

SELECT encoding for External Input Selectors
0b0001

PE Comparator Inputs.

SELECT encoding for PE Comparator Inputs
0b0010

Counters and Sequencer.

SELECT encoding for Counters and Sequencer
0b0011

Single-shot Comparator Controls.

SELECT encoding for Single-shot Comparator Controls
0b0100

Single Address Comparators.

SELECT encoding for Single Address Comparators
0b0101

Address Range Comparators.

SELECT encoding for Address Range Comparators
0b0110

Context Identifier Comparators.

SELECT encoding for Context Identifier Comparators
0b0111

Virtual Context Identifier Comparators.

SELECT encoding for Virtual Context Identifier Comparators

All other values are reserved.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

SELECT, bits [15:0]

Resource Specific Controls. Contains the controls specific to the resource group selected by GROUP, described in the following sections.

SELECT encoding for External Input Selectors
1514131211109876543210
RES0EXTIN[3]EXTIN[2]EXTIN[1]EXTIN[0]

Bits [15:4]

Reserved, RES0.

EXTIN[<m>], bit [m], for m = 3 to 0

Selects one or more External Inputs.

EXTIN[<m>]Meaning
0b0

Ignore EXTIN m.

0b1

Select EXTIN m.

This bit is RES0 if m >= TRCIDR5.NUMEXTINSEL.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

SELECT encoding for PE Comparator Inputs
1514131211109876543210
RES0PECOMP[7]PECOMP[6]PECOMP[5]PECOMP[4]PECOMP[3]PECOMP[2]PECOMP[1]PECOMP[0]

Bits [15:8]

Reserved, RES0.

PECOMP[<m>], bit [m], for m = 7 to 0

Selects one or more PE Comparator Inputs.

PECOMP[<m>]Meaning
0b0

Ignore PE Comparator Input m.

0b1

Select PE Comparator Input m.

This bit is RES0 if m >= TRCIDR4.NUMPC.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

SELECT encoding for Counters and Sequencer
1514131211109876543210
RES0SEQUENCER[3]SEQUENCER[2]SEQUENCER[1]SEQUENCER[0]COUNTERS[3]COUNTERS[2]COUNTERS[1]COUNTERS[0]

Bits [15:8]

Reserved, RES0.

SEQUENCER[<m>], bit [m+4], for m = 3 to 0

Sequencer states.

SEQUENCER[<m>]Meaning
0b0

Ignore Sequencer state m.

0b1

Select Sequencer state m.

This bit is RES0 if m >= TRCIDR5.NUMSEQSTATE.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

COUNTERS[<m>], bit [m], for m = 3 to 0

Counters resources at zero.

COUNTERS[<m>]Meaning
0b0

Ignore Counter m.

0b1

Select Counter m is zero.

This bit is RES0 if m >= TRCIDR5.NUMCNTR.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

SELECT encoding for Single-shot Comparator Controls
1514131211109876543210
RES0SINGLE_SHOT[7]SINGLE_SHOT[6]SINGLE_SHOT[5]SINGLE_SHOT[4]SINGLE_SHOT[3]SINGLE_SHOT[2]SINGLE_SHOT[1]SINGLE_SHOT[0]

Bits [15:8]

Reserved, RES0.

SINGLE_SHOT[<m>], bit [m], for m = 7 to 0

Selects one or more Single-shot Comparator Controls.

SINGLE_SHOT[<m>]Meaning
0b0

Ignore Single-shot Comparator Control m.

0b1

Select Single-shot Comparator Control m.

This bit is RES0 if m >= TRCIDR4.NUMSSCC.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

SELECT encoding for Single Address Comparators
1514131211109876543210
SAC[15]SAC[14]SAC[13]SAC[12]SAC[11]SAC[10]SAC[9]SAC[8]SAC[7]SAC[6]SAC[5]SAC[4]SAC[3]SAC[2]SAC[1]SAC[0]

SAC[<m>], bit [m], for m = 15 to 0

Selects one or more Single Address Comparators.

SAC[<m>]Meaning
0b0

Ignore Single Address Comparator m.

0b1

Select Single Address Comparator m.

This bit is RES0 if m >= 2 × TRCIDR4.NUMACPAIRS.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

SELECT encoding for Address Range Comparators
1514131211109876543210
RES0ARC[7]ARC[6]ARC[5]ARC[4]ARC[3]ARC[2]ARC[1]ARC[0]

Bits [15:8]

Reserved, RES0.

ARC[<m>], bit [m], for m = 7 to 0

Selects one or more Address Range Comparators.

ARC[<m>]Meaning
0b0

Ignore Address Range Comparator m.

0b1

Select Address Range Comparator m.

This bit is RES0 if m >= TRCIDR4.NUMACPAIRS.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

SELECT encoding for Context Identifier Comparators
1514131211109876543210
RES0CID[7]CID[6]CID[5]CID[4]CID[3]CID[2]CID[1]CID[0]

Bits [15:8]

Reserved, RES0.

CID[<m>], bit [m], for m = 7 to 0

Selects one or more Context Identifier Comparators.

CID[<m>]Meaning
0b0

Ignore Context Identifier Comparator m.

0b1

Select Context Identifier Comparator m.

This bit is RES0 if m >= TRCIDR4.NUMCIDC.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

SELECT encoding for Virtual Context Identifier Comparators
1514131211109876543210
RES0VMID[7]VMID[6]VMID[5]VMID[4]VMID[3]VMID[2]VMID[1]VMID[0]
313029282726252423222120191817161514131211109876543210

Bits [15:8]

Reserved, RES0.

VMID[<m>], bit [m], for m = 7 to 0

Selects one or more Virtual Context Identifier Comparators.

VMID[<m>]Meaning
0b0

Ignore Virtual Context Identifier Comparator m.

0b1

Select Virtual Context Identifier Comparator m.

This bit is RES0 if m >= TRCIDR4.NUMVMIDC.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

Accessing the TRCRSCTLR<n>

Must be programmed if any of the following are true:

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

Accesses to this register use the following encodings:

MRS <Xt>, TRCRSCTLR<n>

op0op1CRnCRmop2
0b100b0010b0001n[3:0]0b00:n[4]
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TTA == '1' then
        UNDEFINED;
    elsif CPACR_EL1.TTA == '1' then
        AArch64.SystemAccessTrap(EL1, 0x18);
    elsif EL2Enabled() && CPTR_EL2.TTA == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.TRC == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return TRCRSCTLR[UInt(op2<0>:CRm<3:0>)];
elsif PSTATE.EL == EL2 then
    if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TTA == '1' then
        UNDEFINED;
    elsif CPTR_EL2.TTA == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return TRCRSCTLR[UInt(op2<0>:CRm<3:0>)];
elsif PSTATE.EL == EL3 then
    if CPTR_EL3.TTA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return TRCRSCTLR[UInt(op2<0>:CRm<3:0>)];

MSR TRCRSCTLR<n>, <Xt>

op0op1CRnCRmop2
0b100b0010b0001n[3:0]0b00:n[4]
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TTA == '1' then
        UNDEFINED;
    elsif CPACR_EL1.TTA == '1' then
        AArch64.SystemAccessTrap(EL1, 0x18);
    elsif EL2Enabled() && CPTR_EL2.TTA == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.TRC == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    else
        TRCRSCTLR[UInt(op2<0>:CRm<3:0>)] = X[t];
elsif PSTATE.EL == EL2 then
    if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TTA == '1' then
        UNDEFINED;
    elsif CPTR_EL2.TTA == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    else
        TRCRSCTLR[UInt(op2<0>:CRm<3:0>)] = X[t];
elsif PSTATE.EL == EL3 then
    if CPTR_EL3.TTA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        TRCRSCTLR[UInt(op2<0>:CRm<3:0>)] = X[t];


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