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TRCSTATR, Trace Status Register
The TRCSTATR characteristics are:
Purpose
Returns the trace unit status.
Configuration
AArch64 System register TRCSTATR bits [31:0] are architecturally mapped to External register TRCSTATR[31:0] .
This register is present only when FEAT_ETE is implemented. Otherwise, direct accesses to TRCSTATR are UNDEFINED.
Attributes
TRCSTATR is a 64-bit register.
Field descriptions
The TRCSTATR bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | PMSTABLE | IDLE | |||||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:2]
Reserved, RES0.
PMSTABLE, bit [1]
Programmers' model stable.
| PMSTABLE | Meaning |
|---|---|
| 0b0 |
The programmers' model is not stable. |
| 0b1 |
The programmers' model is stable. |
This bit is UNKNOWN while the trace unit is enabled.
IDLE, bit [0]
Idle status.
| IDLE | Meaning |
|---|---|
| 0b0 |
The trace unit is not idle. |
| 0b1 |
The trace unit is idle. |
Accessing the TRCSTATR
Accesses to this register use the following encodings:
MRS <Xt>, TRCSTATR
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b10 | 0b001 | 0b0000 | 0b0011 | 0b000 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TTA == '1' then
UNDEFINED;
elsif CPACR_EL1.TTA == '1' then
AArch64.SystemAccessTrap(EL1, 0x18);
elsif EL2Enabled() && CPTR_EL2.TTA == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.TRCSTATR == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
return TRCSTATR;
elsif PSTATE.EL == EL2 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TTA == '1' then
UNDEFINED;
elsif CPTR_EL2.TTA == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
return TRCSTATR;
elsif PSTATE.EL == EL3 then
if CPTR_EL3.TTA == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
return TRCSTATR;