TRCVIIECTLR, ViewInst Include/Exclude Control Register
The TRCVIIECTLR characteristics are:
Purpose
Use this to select, or read, the Address Range Comparators for the ViewInst include/exclude function.
Configuration
AArch64 System register TRCVIIECTLR bits [31:0] are architecturally mapped to External register TRCVIIECTLR[31:0] .
This register is present only when FEAT_ETE is implemented and TRCIDR4.NUMACPAIRS > 0b0000. Otherwise, direct accesses to TRCVIIECTLR are UNDEFINED.
Attributes
TRCVIIECTLR is a 64-bit register.
Field descriptions
The TRCVIIECTLR bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | EXCLUDE[7] | EXCLUDE[6] | EXCLUDE[5] | EXCLUDE[4] | EXCLUDE[3] | EXCLUDE[2] | EXCLUDE[1] | EXCLUDE[0] | RES0 | INCLUDE[7] | INCLUDE[6] | INCLUDE[5] | INCLUDE[4] | INCLUDE[3] | INCLUDE[2] | INCLUDE[1] | INCLUDE[0] | ||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:24]
Reserved, RES0.
EXCLUDE[<m>], bit [m+16], for m = 7 to 0
Exclude Address Range Comparator <m>. Selects whether Address Range Comparator <m> is in use with the ViewInst exclude function.
| EXCLUDE[<m>] | Meaning |
|---|---|
| 0b0 |
The address range that Address Range Comparator m defines, is not selected for the ViewInst exclude function. |
| 0b1 |
The address range that Address Range Comparator m defines, is selected for the ViewInst exclude function. |
This bit is RES0 if m >= TRCIDR4.NUMACPAIRS.
On a Trace unit reset, this field resets to an architecturally UNKNOWN value.
Bits [15:8]
Reserved, RES0.
INCLUDE[<m>], bit [m], for m = 7 to 0
Include Address Range Comparator <m>.
Selects whether Address Range Comparator <m> is in use with the ViewInst include function.
Selecting no comparators for the ViewInst include function indicates that all instructions are included by default.
The ViewInst exclude function then indicates which ranges are excluded.
| INCLUDE[<m>] | Meaning |
|---|---|
| 0b0 |
The address range that Address Range Comparator m defines, is not selected for the ViewInst include function. |
| 0b1 |
The address range that Address Range Comparator m defines, is selected for the ViewInst include function. |
This bit is RES0 if m >= TRCIDR4.NUMACPAIRS.
On a Trace unit reset, this field resets to an architecturally UNKNOWN value.
Accessing the TRCVIIECTLR
Must be programmed if TRCIDR4.NUMACPAIRS > 0b0000.
Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.
Accesses to this register use the following encodings:
MRS <Xt>, TRCVIIECTLR
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b10 | 0b001 | 0b0000 | 0b0001 | 0b010 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TTA == '1' then
UNDEFINED;
elsif CPACR_EL1.TTA == '1' then
AArch64.SystemAccessTrap(EL1, 0x18);
elsif EL2Enabled() && CPTR_EL2.TTA == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.TRC == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
return TRCVIIECTLR;
elsif PSTATE.EL == EL2 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TTA == '1' then
UNDEFINED;
elsif CPTR_EL2.TTA == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
return TRCVIIECTLR;
elsif PSTATE.EL == EL3 then
if CPTR_EL3.TTA == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
return TRCVIIECTLR;
MSR TRCVIIECTLR, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b10 | 0b001 | 0b0000 | 0b0001 | 0b010 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TTA == '1' then
UNDEFINED;
elsif CPACR_EL1.TTA == '1' then
AArch64.SystemAccessTrap(EL1, 0x18);
elsif EL2Enabled() && CPTR_EL2.TTA == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.TRC == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
TRCVIIECTLR = X[t];
elsif PSTATE.EL == EL2 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TTA == '1' then
UNDEFINED;
elsif CPTR_EL2.TTA == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
TRCVIIECTLR = X[t];
elsif PSTATE.EL == EL3 then
if CPTR_EL3.TTA == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
TRCVIIECTLR = X[t];