VMPIDR_EL2, Virtualization Multiprocessor ID Register
The VMPIDR_EL2 characteristics are:
Purpose
Holds the value of the Virtualization Multiprocessor ID. This is the value returned by EL1 reads of MPIDR_EL1.
Configuration
AArch64 System register VMPIDR_EL2 bits [31:0] are architecturally mapped to AArch32 System register VMPIDR[31:0] .
If EL2 is not implemented, reads of this register return the value of the MPIDR_EL1 and writes to the register are ignored.
This register has no effect if EL2 is not enabled in the current Security state.
Attributes
VMPIDR_EL2 is a 64-bit register.
Field descriptions
The VMPIDR_EL2 bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| RES0 | Aff3 | ||||||||||||||||||||||||||||||
| RES1 | U | RES0 | MT | Aff2 | Aff1 | Aff0 | |||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:40]
Reserved, RES0.
Aff3, bits [39:32]
Affinity level 3. See the description of VMPIDR_EL2.Aff0 for more information.
Aff3 is not supported in AArch32 state.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Bit [31]
Reserved, RES1.
U, bit [30]
Indicates a Uniprocessor system, as distinct from PE 0 in a multiprocessor system.
| U | Meaning |
|---|---|
| 0b0 |
Processor is part of a multiprocessor system. |
| 0b1 |
Processor is part of a uniprocessor system. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Bits [29:25]
Reserved, RES0.
MT, bit [24]
Indicates whether the lowest level of affinity consists of logical PEs that are implemented using a multithreading type approach. See the description of VMPIDR_EL2.Aff0 for more information about affinity levels.
| MT | Meaning |
|---|---|
| 0b0 |
Performance of PEs at the lowest affinity level is largely independent. |
| 0b1 |
Performance of PEs at the lowest affinity level is very interdependent. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Aff2, bits [23:16]
Affinity level 2. See the description of VMPIDR_EL2.Aff0 for more information.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Aff1, bits [15:8]
Affinity level 1. See the description of VMPIDR_EL2.Aff0 for more information.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Aff0, bits [7:0]
Affinity level 0. This is the affinity level that is most significant for determining PE behavior. Higher affinity levels are increasingly less significant in determining PE behavior. The assigned value of the MPIDR.{Aff2, Aff1, Aff0} or MPIDR_EL1.{Aff3, Aff2, Aff1, Aff0} set of fields of each PE must be unique within the system as a whole.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Accessing the VMPIDR_EL2
Accesses to this register use the following encodings:
MRS <Xt>, VMPIDR_EL2
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b100 | 0b0000 | 0b0000 | 0b101 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then
return NVMem[0x050];
elsif EL2Enabled() && HCR_EL2.NV == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
return VMPIDR_EL2;
elsif PSTATE.EL == EL3 then
if !HaveEL(EL2) then
return MPIDR_EL1;
else
return VMPIDR_EL2;
MSR VMPIDR_EL2, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b100 | 0b0000 | 0b0000 | 0b101 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then
NVMem[0x050] = X[t];
elsif EL2Enabled() && HCR_EL2.NV == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
VMPIDR_EL2 = X[t];
elsif PSTATE.EL == EL3 then
if !HaveEL(EL2) then
//no operation
else
VMPIDR_EL2 = X[t];
MRS <Xt>, MPIDR_EL1
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b0000 | 0b0000 | 0b101 |
if PSTATE.EL == EL0 then
if IsFeatureImplemented(FEAT_IDST) then
if EL2Enabled() && HCR_EL2.TGE == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
AArch64.SystemAccessTrap(EL1, 0x18);
else
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.MPIDR_EL1 == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() then
return VMPIDR_EL2;
else
return MPIDR_EL1;
elsif PSTATE.EL == EL2 then
return MPIDR_EL1;
elsif PSTATE.EL == EL3 then
return MPIDR_EL1;