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EDLSR, External Debug Lock Status Register

The EDLSR characteristics are:


Indicates the current status of the software lock for external debug registers.

The optional Software Lock provides a lock to prevent memory-mapped writes to the debug registers. Use of this lock mechanism reduces the risk of accidental damage to the contents of the debug registers. It does not, and cannot, prevent all accidental or malicious damage.


If FEAT_DoPD is implemented, Software Lock is not implemented by the architecturally-defined debug components of the PE in the Core power domain.

If FEAT_DoPD is not implemented, this register is in the Debug power domain.

Software uses EDLAR to set or clear the lock, and EDLSR to check the current status of the lock.


EDLSR is a 32-bit register.

Field descriptions

The EDLSR bit assignments are:


Bits [31:3]

Reserved, RES0.

nTT, bit [2]

Not thirty-two bit access required. RAZ.

SLK, bit [1]

When Software Lock is implemented:

Software Lock status for this component. For an access to LSR that is not a memory-mapped access, or when Software Lock is not implemented, this field is RES0.

For memory-mapped accesses when Software Lock is implemented, possible values of this field are:


Lock clear. Writes are permitted to this component's registers.


Lock set. Writes to this component's registers are ignored, and reads have no side effects.

On a Cold reset, when FEAT_DoPD is implemented, this field resets to 1.

On an External debug reset, when FEAT_DoPD is not implemented, this field resets to 1.


Reserved, RAZ.

SLI, bit [0]

Software Lock implemented. For an access to LSR that is not a memory-mapped access, this field is RAZ. For memory-mapped accesses, the value of this field is IMPLEMENTATION DEFINED. Permitted values are:


Software Lock not implemented or not memory-mapped access.


Software Lock implemented and memory-mapped access.

Accessing the EDLSR

EDLSR can be accessed through the memory-mapped interfaces:


This interface is accessible as follows:

  • When FEAT_DoPD is not implemented or IsCorePowered() accesses to this register are RO.
  • Otherwise accesses to this register generate an error response.