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ERRCRICR2, Critical Error Interrupt Configuration Register 2

The ERRCRICR2 characteristics are:

Purpose

Critical Error Interrupt control and configuration register.

Configuration

This register is present only when (the Critical Error Interrupt is implemented or the implementation does not use the recommended layout for the ERRIRQCR<n> registers) and interrupt configuration registers are implemented. Otherwise, direct accesses to ERRCRICR2 are RES0.

ERRCRICR2 is implemented only as part of a memory-mapped group of error records.

Attributes

ERRCRICR2 is a 32-bit register.

Field descriptions

The ERRCRICR2 bit assignments are:

When the Critical Error Interrupt is implemented and the implementation uses the recommended layout for the ERRIRQCR<n> registers:
313029282726252423222120191817161514131211109876543210
RES0IRQENNSMSISHMemAttr

Bits [31:8]

Reserved, RES0.

IRQEN, bit [7]

When the component supports disabling message signaled interrupts:

Message signaled interrupt enable. Enables generation of message signaled interrupts.

IRQENMeaning
0b0

Disabled.

0b1

Enabled.

On an Error recovery reset, this field resets to 0.


Otherwise:

Reserved, RES0.

Message signaled interrupt enable.

Message signaled interrupts are always enabled.

NSMSI, bit [6]

When the component supports configuring the Security attribute for message signaled interrupts and the component does not allow Non-secure writes to ERRCRICR2:

Security attribute. Defines the physical address space for message signaled interrupts.

NSMSIMeaning
0b0

Secure.

0b1

Non-secure.

On an Error recovery reset, this field resets to an IMPLEMENTATION DEFINED value.


When the component allows Non-secure writes to ERRCRICR2:

Reserved, RES0.

Security attribute. Defines the physical address space for message signaled interrupts.

The Security attribute used for message signaled interrupts is Non-secure.


Otherwise:

Reserved, RES0.

Security attribute. Defines the physical address space for message signaled interrupts.

The Security attribute for message signaled interrupts is IMPLEMENTATION DEFINED.

SH, bits [5:4]

When the component supports configuring the Shareability domain:

Shareability. Defines the Shareability domain for message signaled interrupts.

SHMeaning
0b00

Not shared.

0b10

Outer Shareable.

0b11

Inner Shareable.

All other values are reserved.

This field is ignored when ERRCRICR2.MemAttr specifies any of the following memory types:

  • Any Device memory type.
  • Normal memory, Inner Non-cacheable, Outer Non-cacheable.

All Device and Normal Inner Non-cacheable Outer Non-cacheable memory regions are always treated as Outer Shareable.

On an Error recovery reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

Shareability.

The Shareability domain for message signaled interrupts is IMPLEMENTATION DEFINED.

MemAttr, bits [3:0]

When the component supports configuring the memory type for message signaled interrupts:

Memory type. Defines the memory type and attributes for message signaled interrupts.

MemAttrMeaning
0b0000

Device-nGnRnE memory.

0b0001

Device-nGnRE memory.

0b0010

Device-nGRE memory.

0b0011

Device-GRE memory.

0b0101

Normal memory, Inner Non-cacheable, Outer Non-cacheable.

0b0110

Normal memory, Inner Write-Through, Outer Non-cacheable.

0b0111

Normal memory, Inner Write-Back, Outer Non-cacheable.

0b1001

Normal memory, Inner Non-cacheable, Outer Write-Through.

0b1010

Normal memory, Inner Write-Through, Outer Write-Through.

0b1011

Normal memory, Inner Write-Back, Outer Write-Through.

0b1101

Normal memory, Inner Non-cacheable, Outer Write-Back.

0b1110

Normal memory, Inner Write-Through, Outer Write-Back.

0b1111

Normal memory, Inner Write-Back, Outer Write-Back.

All other values are reserved.

Note

This is the same format as the VMSAv8-64 stage 2 memory region attributes.

On an Error recovery reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

Memory type.

The memory type used for message signaled interrupts is IMPLEMENTATION DEFINED.

When the implementation does not use the recommended layout for the ERRIRQCR<n> registers:
313029282726252423222120191817161514131211109876543210
IMPLEMENTATION DEFINED

IMPLEMENTATION DEFINED, bits [31:0]

IMPLEMENTATION DEFINED.

Accessing the ERRCRICR2

ERRCRICR2 can be accessed through the memory-mapped interfaces:

ComponentOffset
RAS0xEAC

Accesses on this interface are RW.