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ERR<n>STATUS, Error Record Primary Status Register, n = 0 - 65534

The ERR<n>STATUS characteristics are:

Purpose

Contains status information for error record <n>, including:

  • Whether any error has been detected (valid).
  • Whether any detected error was not corrected, and returned to a Requester.
  • Whether any detected error was not corrected and deferred.
  • Whether an error record has been discarded because additional errors have been detected before the first error was handled by software (overflow).
  • Whether any error has been reported.
  • Whether the other error record registers contain valid information.
  • Whether the error was reported because poison data was detected or because a corrupt value was detected by an error detection code.
  • A primary error code.
  • An IMPLEMENTATION DEFINED extended error code.

Within this register:

  • The {AV, V, MV} bits are valid bits that define whether error record <n> registers are valid.
  • The {UE, OF, CE, DE, UET} bits encode the types of error or errors recorded.
  • The {CI, ER, PN, IERR, SERR} fields are syndrome fields.

Configuration

This register is present only when error record <n> is implemented. Otherwise, direct accesses to ERR<n>STATUS are RES0.

ERR<q>FR describes the features implemented by the node that owns error record <n>. <q> is the index of the first error record owned by the same node as error record <n>. If the node owns a single record, then q = n.

For IMPLEMENTATION DEFINED fields in ERR<n>STATUS, writing zero returns the error record to an initial quiescent state.

In particular, if any IMPLEMENTATION DEFINED syndrome fields might generate a Fault Handling or Error Recovery Interrupt request, writing zero is sufficient to deactivate the Interrupt request.

Fields that are read-only, non-zero, and ignore writes are compliant with this requirement.

Note

Arm recommends that any IMPLEMENTATION DEFINED syndrome field that can generate a Fault Handling, Error Recovery, Critical, or IMPLEMENTATION DEFINED, interrupt request is disabled at Cold reset and is enabled by software writing an IMPLEMENTATION DEFINED nonzero value to an IMPLEMENTATION DEFINED field in ERR<q>CTLR.

Attributes

ERR<n>STATUS is a 64-bit register.

Field descriptions

The ERR<n>STATUS bit assignments are:

When RAS System Architecture v1.1 is implemented:
6362616059585756555453525150494847464544434241403938373635343332
RES0
AVVUEEROFMVCEDEPNUETCIRES0IERRSERR

Bits [63:32]

Reserved, RES0.

AV, bit [31]

When error record <n> includes an address associated with an error:

Address Valid.

AVMeaning
0b0

ERR<n>ADDR not valid.

0b1

ERR<n>ADDR contains an address associated with the highest priority error recorded by this record.

This bit is read/write-one-to-clear.

On a Cold reset, this field resets to 0.


Otherwise:

Reserved, RES0.

V, bit [30]

Status Register Valid.

VMeaning
0b0

ERR<n>STATUS not valid.

0b1

ERR<n>STATUS valid. At least one error has been recorded.

This bit is read/write-one-to-clear.

On a Cold reset, this field resets to 0.

UE, bit [29]

Uncorrected Error.

UEMeaning
0b0

No errors have been detected, or all detected errors have been either corrected or deferred.

0b1

At least one detected error was not corrected and not deferred.

When clearing ERR<n>STATUS.V to 0b0, if this bit is nonzero, then Arm recommends that software write 0b1 to this bit to clear this bit to zero.

This bit is not valid and reads UNKNOWN if ERR<n>STATUS.V == 0b0.

This bit is read/write-one-to-clear.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

ER, bit [28]

Error Reported.

ERMeaning
0b0

No in-band error (External Abort) reported.

0b1

An External Abort was signaled by the component to the Requester making the access or other transaction. This can be because any of the following are true:

  • The applicable one of the ERR<q>CTLR.{WUE,RUE,UE} bits is implemented and was set to 0b1 when an Uncorrected error was detected.
  • The applicable one of the ERR<q>CTLR.{WUE,RUE,UE} bits is not implemented and the component always reports errors.

It is IMPLEMENTATION DEFINED whether this bit can be set to 0b1 by a Deferred error.

When clearing ERR<n>STATUS.V to 0b0, if this bit is nonzero, then Arm recommends that software write 0b1 to this bit to clear this bit to zero.

This bit is not valid and reads UNKNOWN if any of the following are true:

  • ERR<n>STATUS.V == 0b0.
  • ERR<n>STATUS.UE == 0b0 and this bit is never set to 0b1 by a Deferred error.
  • ERR<n>STATUS.{UE,DE} == {0,0} and this bit can be set to 0b1 by a Deferred error.

This bit is read/write-one-to-clear.

Note

An External Abort signaled by the component might be masked and not generate any exception.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

OF, bit [27]

Overflow.

Indicates that multiple errors have been detected. This bit is set to 0b1 when one of the following occurs:

  • A Corrected error counter is implemented, an error is counted, and the counter overflows.
  • ERR<n>STATUS.V was previously set to 0b1, a Corrected error counter is not implemented, and a Corrected error is recorded.
  • ERR<n>STATUS.V was previously set to 0b1, and a type of error other than a Corrected error is recorded.

Otherwise, this bit is unchanged when an error is recorded.

If a Corrected error counter is implemented:

  • A direct write that modifies the counter overflow flag indirectly might set this bit to an UNKNOWN value.
  • A direct write to this bit that clears this bit to zero might indirectly set the counter overflow flag to an UNKNOWN value.
OFMeaning
0b0

Since this bit was last cleared to zero, no error syndrome has been discarded and, if a Corrected error counter is implemented, it has not overflowed.

0b1

Since this bit was last cleared to zero, at least one error syndrome has been discarded or, if a Corrected error counter is implemented, it might have overflowed.

When clearing ERR<n>STATUS.V to 0b0, if this bit is nonzero, then Arm recommends that software write 0b1 to this bit to clear this bit to zero.

This bit is not valid and reads UNKNOWN if ERR<n>STATUS.V == 0b0.

This bit is read/write-one-to-clear.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

MV, bit [26]

When error record <n> includes an additional information for an error:

Miscellaneous Registers Valid.

MVMeaning
0b0

ERR<n>MISC<m> not valid.

0b1

The IMPLEMENTATION DEFINED contents of the ERR<n>MISC<m> registers contains additional information for an error recorded by this record.

This bit is read/write-one-to-clear.

Note

If the ERR<n>MISC<m> registers can contain additional information for a previously recorded error, then the contents must be self-describing to software or a user. For example, certain fields might relate only to Corrected errors, and other fields only to the most recent error that was not discarded.

On a Cold reset, this field resets to 0.


Otherwise:

Reserved, RES0.

CE, bits [25:24]

Corrected Error.

CEMeaning
0b00

No errors were corrected.

0b01

At least one transient error was corrected.

0b10

At least one error was corrected.

0b11

At least one persistent error was corrected.

The mechanism by which a component or node detects whether a correctable error is transient or persistent is IMPLEMENTATION DEFINED. If no such mechanism is implemented, then the node sets this field to 0b10 when a corrected error is recorded.

When clearing ERR<n>STATUS.V to 0b0, if this field is nonzero, then Arm recommends that software write ones to this field to clear this field to zero.

This field is not valid and reads UNKNOWN if ERR<n>STATUS.V == 0b0.

This field is read/write-ones-to-clear. Writing a value other than all-zeros or all-ones sets this field to an UNKNOWN value.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

DE, bit [23]

Deferred Error.

DEMeaning
0b0

No errors were deferred.

0b1

At least one error was not corrected and deferred.

Support for deferring errors is IMPLEMENTATION DEFINED.

When clearing ERR<n>STATUS.V to 0b0, if this bit is nonzero, then Arm recommends that software write 0b1 to this bit to clear this bit to zero.

This bit is not valid and reads UNKNOWN if ERR<n>STATUS.V == 0b0.

This bit is read/write-one-to-clear.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

PN, bit [22]

Poison.

PNMeaning
0b0

Uncorrected error or Deferred error recorded because a corrupt value was detected, for example, by an error detection code (EDC), or Corrected error recorded.

0b1

Uncorrected error or Deferred error recorded because a poison value was detected.

When clearing ERR<n>STATUS.V to 0b0, if this bit is nonzero, then Arm recommends that software write 0b1 to this bit to clear this bit to zero.

This bit is not valid and reads UNKNOWN if any of the following are true:

  • ERR<n>STATUS.V == 0b0.
  • ERR<n>STATUS.{DE,UE} == {0,0}.

This bit is read/write-one-to-clear.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

UET, bits [21:20]

Uncorrected Error Type. Describes the state of the component after detecting or consuming an Uncorrected error.

UETMeaning
0b00

Uncorrected error, Uncontainable error (UC).

0b01

Uncorrected error, Unrecoverable error (UEU).

0b10

Uncorrected error, Latent or Restartable error (UEO).

0b11

Uncorrected error, Signaled or Recoverable error (UER).

When clearing ERR<n>STATUS.V to 0b0, if this field is nonzero, then Arm recommends that software write ones to this field to clear this field to zero.

This field is not valid and reads UNKNOWN if any of the following are true:

  • ERR<n>STATUS.V == 0b0.
  • ERR<n>STATUS.UE == 0b0.

This field is read/write-ones-to-clear. Writing a value other than all-zeros or all-ones sets this field to an UNKNOWN value.

Note

Software might use the information in the error record registers to determine what recovery is necessary.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

CI, bit [19]

Critical Error. Indicates whether a critical error condition has been recorded.

CIMeaning
0b0

No critical error condition.

0b1

Critical error condition.

When clearing ERR<n>STATUS.V to 0b0, if this bit is nonzero, then Arm recommends that software write 0b1 to this bit to clear this bit to zero.

This bit is not valid and reads UNKNOWN if ERR<n>STATUS.V == 0b0.

This bit is read/write-one-to-clear.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Bits [18:16]

Reserved, RES0.

IERR, bits [15:8]

IMPLEMENTATION DEFINED error code. Used with any primary error code ERR<n>STATUS.SERR value. Further IMPLEMENTATION DEFINED information can be placed in the ERR<n>MISC<m> registers.

The implemented set of valid values that this field can take is IMPLEMENTATION DEFINED. If any value not in this set is written to this register, then the value read back from this field is UNKNOWN.

Note

This means that one or more bits of this field might be implemented as fixed read-as-zero or read-as-one values.

This field is not valid and reads UNKNOWN if all of the following are true:

  • Any of the following are true:
    • The RAS Common Fault Injection Model Extension is implemented by the node that owns this error record and ERR<q>PFGF.SYN == 0b0.
    • The RAS Common Fault Injection Model Extension is not implemented by the node that owns this error record.
  • ERR<n>STATUS.V == 0b0.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

SERR, bits [7:0]

Architecturally-defined primary error code. The primary error code might be used by a fault handling agent to triage an error without requiring device-specific code. For example, to count and threshold corrected errors in software, or generate a short log entry.

SERRMeaning
0x00

No error.

0x01

IMPLEMENTATION DEFINED error.

0x02

Data value from (non-associative) internal memory. For example, ECC from on-chip SRAM or buffer.

0x03

IMPLEMENTATION DEFINED pin. For example, nSEI pin.

0x04

Assertion failure. For example, consistency failure.

0x05

Error detected on internal data path. For example, parity on ALU result.

0x06

Data value from associative memory. For example, ECC error on cache data.

0x07

Address/control value from associative memory. For example, ECC error on cache tag.

0x08

Data value from a TLB. For example, ECC error on TLB data.

0x09

Address/control value from a TLB. For example, ECC error on TLB tag.

0x0A

Data value from producer. For example, parity error on write data bus.

0x0B

Address/control value from producer. For example, parity error on address bus.

0x0C

Data value from (non-associative) external memory. For example, ECC error in SDRAM.

0x0D

Illegal address (software fault). For example, access to unpopulated memory.

0x0E

Illegal access (software fault). For example, byte write to word register.

0x0F

Illegal state (software fault). For example, device not ready.

0x10

Internal data register. For example, parity on a SIMD&FP register. For a PE, all general-purpose, stack pointer, SIMD&FP, and SVE registers are data registers.

0x11

Internal control register. For example, Parity on a System register. For a PE, all registers other than general-purpose, stack pointer, SIMD&FP, and SVE registers are control registers.

0x12

Error response from Completer of access. For example, error response from cache write-back.

0x13

External timeout. For example, timeout on interaction with another component.

0x14

Internal timeout. For example, timeout on interface within the component.

0x15

Deferred error from Completer not supported at Requester. For example, poisoned data received from the Completer of an access by a Requester that cannot defer the error further.

0x16

Deferred error from Requester not supported at Completer. For example, poisoned data received from the Requester of an access by a Completer that cannot defer the error further.

0x17

Deferred error from Completer passed through. For example, poisoned data received from the Completer of an access and returned to the Requester.

0x18

Deferred error from Requester passed through. For example, poisoned data received from the Requester of an access and deferred to the Completer.

0x19

Error recorded by PCIe error logs. Indicates that the component has recorded an error in a PCIe error log. This might be the PCIe device status register, AER, DVSEC, or other mechanisms defined by PCIe.

All other values are reserved.

The implemented set of valid values that this field can take is IMPLEMENTATION DEFINED. If any value not in this set is written to this register, then the value read back from this field is UNKNOWN.

Note

This means that one or more bits of this field might be implemented as fixed read-as-zero or read-as-one values.

This field is not valid and reads UNKNOWN if all of the following are true:

  • Any of the following are true:
    • The RAS Common Fault Injection Model Extension is implemented by the node that owns this error record and ERR<q>PFGF.SYN == 0b0.
    • The RAS Common Fault Injection Model Extension is not implemented by the node that owns this error record.
  • ERR<n>STATUS.V == 0b0.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

When RAS System Architecture v1.0 is implemented:
6362616059585756555453525150494847464544434241403938373635343332
RES0
AVVUEEROFMVCEDEPNUETRES0IERRSERR
313029282726252423222120191817161514131211109876543210
313029282726252423222120191817161514131211109876543210

Bits [63:32]

Reserved, RES0.

AV, bit [31]

When error record <n> includes an address associated with an error:

Address Valid.

AVMeaning
0b0

ERR<n>ADDR not valid.

0b1

ERR<n>ADDR contains an address associated with the highest priority error recorded by this record.

This bit ignores writes if ERR<n>STATUS.{CE,DE,UE} != {0b00,0,0}, and the highest priority of these is not being cleared to zero in the same write.

This bit is read/write-one-to-clear.

On a Cold reset, this field resets to 0.


Otherwise:

Reserved, RES0.

V, bit [30]

Status Register Valid.

VMeaning
0b0

ERR<n>STATUS not valid.

0b1

ERR<n>STATUS valid. At least one error has been recorded.

This bit ignores writes if ERR<n>STATUS.{CE,DE,UE} != {0b00,0,0}, and is not being cleared to 0b0 in the same write.

This bit is read/write-one-to-clear.

On a Cold reset, this field resets to 0.

UE, bit [29]

Uncorrected Error.

UEMeaning
0b0

No errors have been detected, or all detected errors have been either corrected or deferred.

0b1

At least one detected error was not corrected and not deferred.

When clearing ERR<n>STATUS.V to 0b0, if this bit is nonzero, then Arm recommends that software write 0b1 to this bit to clear this bit to zero.

This bit is not valid and reads UNKNOWN if ERR<n>STATUS.V == 0b0. This bit ignores writes if ERR<n>STATUS.OF == 0b1 and is not being cleared to 0b0 in the same write.

This bit is read/write-one-to-clear.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

ER, bit [28]

Error Reported.

ERMeaning
0b0

No in-band error (External Abort) reported.

0b1

An External Abort was signaled by the component to the Requester making the access or other transaction. This can be because any of the following are true:

  • The applicable one of the ERR<q>CTLR.{WUE,RUE,UE} bits is implemented and was set to 0b1 when an Uncorrected error was detected.
  • The applicable one of the ERR<q>CTLR.{WUE,RUE,UE} bits is not implemented and the component always reports errors.

It is IMPLEMENTATION DEFINED whether this bit can be set to 0b1 by a Deferred error.

If this bit is nonzero, then Arm recommends that software write 0b1 to this bit to clear this bit to zero, when any of:

  • Clearing ERR<n>STATUS.V to 0b0.
  • Clearing ERR<n>STATUS.UE to 0b0, if this bit is never set to 0b1 by a Deferred error.
  • Clearing ERR<n>STATUS.{UE,DE} to {0,0}, if this bit can be set to 0b1 by a Deferred error.

This bit is not valid and reads UNKNOWN if any of the following are true:

  • ERR<n>STATUS.V == 0b0.
  • ERR<n>STATUS.UE == 0b0 and this bit is never set to 0b1 by a Deferred error.
  • ERR<n>STATUS.{UE,DE} == {0,0} and this bit can be set to 0b1 by a Deferred error.

This bit ignores writes if ERR<n>STATUS.{CE,DE,UE} != {0b00,0,0}, and the highest priority of these is not being cleared to zero in the same write.

This bit is read/write-one-to-clear.

Note

An External Abort signaled by the component might be masked and not generate any exception.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

OF, bit [27]

Overflow.

Indicates that multiple errors have been detected. This bit is set to 0b1 when one of the following occurs:

  • An Uncorrected error is detected and ERR<n>STATUS.UE == 0b1.
  • A Deferred error is detected, ERR<n>STATUS.UE == 0b0 and ERR<n>STATUS.DE == 0b1.
  • A Corrected error is detected, no Corrected error counter is implemented, ERR<n>STATUS.UE == 0b0, ERR<n>STATUS.DE == 0b0, and ERR<n>STATUS.CE != 0b00. ERR<n>STATUS.CE might be updated for the new Corrected error.
  • A Corrected error counter is implemented, ERR<n>STATUS.UE == 0b0, ERR<n>STATUS.DE == 0b0, and the counter overflows.

It is IMPLEMENTATION DEFINED whether this bit is set to 0b1 when one of the following occurs:

  • A Deferred error is detected and ERR<n>STATUS.UE == 0b1.
  • A Corrected error is detected, no Corrected error counter is implemented, and either or both the ERR<n>STATUS.UE or ERR<n>STATUS.DE bits are set to 0b1.
  • A Corrected error counter is implemented, either or both the ERR<n>STATUS.UE or ERR<n>STATUS.DE bits are set to 0b1, and the counter overflows.

It is IMPLEMENTATION DEFINED whether this bit is cleared to 0b0 when one of the following occurs:

  • An Uncorrected error is detected and ERR<n>STATUS.UE == 0b0.
  • A Deferred error is detected, ERR<n>STATUS.UE == 0b0 and ERR<n>STATUS.DE == 0b0.
  • A Corrected error is detected, ERR<n>STATUS.UE == 0b0, ERR<n>STATUS.DE == 0b0 and ERR<n>STATUS.CE == 0b00.

The IMPLEMENTATION DEFINED clearing of this bit might also depend on the value of the other error status bits.

If a Corrected error counter is implemented:

  • A direct write that modifies the counter overflow flag indirectly might set this bit to an UNKNOWN value.
  • A direct write to this bit that clears this bit to 0b0 might indirectly set the counter overflow flag to an UNKNOWN value.
OFMeaning
0b0

If ERR<n>STATUS.UE == 0b1, then no error syndrome for an Uncorrected error has been discarded.

If ERR<n>STATUS.UE == 0b0 and ERR<n>STATUS.DE == 0b1, then no error syndrome for a Deferred error has been discarded.

If ERR<n>STATUS.UE == 0b0, ERR<n>STATUS.DE == 0b0, and a Corrected error counter is implemented, then the counter has not overflowed.

If ERR<n>STATUS.UE == 0b0, ERR<n>STATUS.DE == 0b0, ERR<n>STATUS.CE != 0b00, and no Corrected error counter is implemented, then no error syndrome for a Corrected error has been discarded.

Note

This bit might have been set to 0b1 when an error syndrome was discarded and later cleared to 0b0 when a higher priority syndrome was recorded.

0b1

At least one error syndrome has been discarded or, if a Corrected error counter is implemented, it might have overflowed.

When clearing ERR<n>STATUS.V to 0b0, if this bit is nonzero, then Arm recommends that software write 0b1 to this bit to clear this bit to zero.

This bit is not valid and reads UNKNOWN if ERR<n>STATUS.V == 0b0.

This bit is read/write-one-to-clear.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

MV, bit [26]

When error record <n> includes an additional information for an error:

Miscellaneous Registers Valid.

MVMeaning
0b0

ERR<n>MISC<m> not valid.

0b1

The IMPLEMENTATION DEFINED contents of the ERR<n>MISC<m> registers contains additional information for an error recorded by this record.

This bit ignores writes if ERR<n>STATUS.{CE,DE,UE} != {0b00,0,0}, and the highest priority of these is not being cleared to zero in the same write.

This bit is read/write-one-to-clear.

Note

If the ERR<n>MISC<m> registers can contain additional information for a previously recorded error, then the contents must be self-describing to software or a user. For example, certain fields might relate only to Corrected errors, and other fields only to the most recent error that was not discarded.

On a Cold reset, this field resets to 0.


Otherwise:

Reserved, RES0.

CE, bits [25:24]

Corrected Error.

CEMeaning
0b00

No errors were corrected.

0b01

At least one transient error was corrected.

0b10

At least one error was corrected.

0b11

At least one persistent error was corrected.

The mechanism by which a component or node detects whether a correctable error is transient or persistent is IMPLEMENTATION DEFINED. If no such mechanism is implemented, then the node sets this field to 0b10 when a corrected error is recorded.

When clearing ERR<n>STATUS.V to 0b0, if this field is nonzero, then Arm recommends that software write ones to this field to clear this field to zero.

This field is not valid and reads UNKNOWN if ERR<n>STATUS.V == 0b0. This field ignores writes if ERR<n>STATUS.OF == 0b1 and is not being cleared to 0b0 in the same write.

This field is read/write-ones-to-clear. Writing a value other than all-zeros or all-ones sets this field to an UNKNOWN value.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

DE, bit [23]

Deferred Error.

DEMeaning
0b0

No errors were deferred.

0b1

At least one error was not corrected and deferred.

Support for deferring errors is IMPLEMENTATION DEFINED.

When clearing ERR<n>STATUS.V to 0b0, if this bit is nonzero, then Arm recommends that software write 0b1 to this bit to clear this bit to zero.

This bit is not valid and reads UNKNOWN if ERR<n>STATUS.V == 0b0. This bit ignores writes if ERR<n>STATUS.OF == 0b1 and is not being cleared to 0b0 in the same write.

This bit is read/write-one-to-clear.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

PN, bit [22]

Poison.

PNMeaning
0b0

Uncorrected error or Deferred error recorded because a corrupt value was detected, for example, by an error detection code (EDC), or Corrected error recorded.

0b1

Uncorrected error or Deferred error recorded because a poison value was detected.

If this bit is nonzero, then Arm recommends that software write 0b1 to this bit to clear this bit to zero, when any of:

  • Clearing ERR<n>STATUS.V to 0b0.
  • Clearing both ERR<n>STATUS.{DE, UE} to 0b0.

This bit is not valid and reads UNKNOWN if any of the following are true:

  • ERR<n>STATUS.V == 0b0.
  • ERR<n>STATUS.{DE,UE} == {0,0}.

This bit ignores writes if ERR<n>STATUS.{CE,DE,UE} != {0b00,0,0}, and the highest priority of these is not being cleared to zero in the same write.

This bit is read/write-one-to-clear.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

UET, bits [21:20]

Uncorrected Error Type. Describes the state of the component after detecting or consuming an Uncorrected error.

UETMeaning
0b00

Uncorrected error, Uncontainable error (UC).

0b01

Uncorrected error, Unrecoverable error (UEU).

0b10

Uncorrected error, Latent or Restartable error (UEO).

0b11

Uncorrected error, Signaled or Recoverable error (UER).

If this field is nonzero, then Arm recommends that software write ones to this field to clear this field to zero, when any of:

  • Clearing ERR<n>STATUS.V to 0b0.
  • Clearing ERR<n>STATUS.UE to 0b0.

This field is not valid and reads UNKNOWN if any of the following are true:

  • ERR<n>STATUS.V == 0b0.
  • ERR<n>STATUS.UE == 0b0.

This field ignores writes if ERR<n>STATUS.{CE,DE,UE} != {0b00,0,0}, and the highest priority of these is not being cleared to zero in the same write.

This field is read/write-ones-to-clear. Writing a value other than all-zeros or all-ones sets this field to an UNKNOWN value.

Note

Software might use the information in the error record registers to determine what recovery is necessary.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Bits [19:16]

Reserved, RES0.

IERR, bits [15:8]

IMPLEMENTATION DEFINED error code. Used with any primary error code ERR<n>STATUS.SERR value. Further IMPLEMENTATION DEFINED information can be placed in the ERR<n>MISC<m> registers.

The implemented set of valid values that this field can take is IMPLEMENTATION DEFINED. If any value not in this set is written to this register, then the value read back from this field is UNKNOWN.

Note

This means that one or more bits of this field might be implemented as fixed read-as-zero or read-as-one values.

This field is not valid and reads UNKNOWN if all of the following are true:

  • Any of the following are true:
    • The RAS Common Fault Injection Model Extension is implemented by the node that owns this error record and ERR<q>PFGF.SYN == 0b0.
    • The RAS Common Fault Injection Model Extension is not implemented by the node that owns this error record.
  • ERR<n>STATUS.V == 0b0.

This field ignores writes if ERR<n>STATUS.{CE,DE,UE} != {0b00,0,0}, and the highest priority of these is not being cleared to zero in the same write.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

SERR, bits [7:0]

Architecturally-defined primary error code. The primary error code might be used by a fault handling agent to triage an error without requiring device-specific code. For example, to count and threshold corrected errors in software, or generate a short log entry.

SERRMeaning
0x00

No error.

0x01

IMPLEMENTATION DEFINED error.

0x02

Data value from (non-associative) internal memory. For example, ECC from on-chip SRAM or buffer.

0x03

IMPLEMENTATION DEFINED pin. For example, nSEI pin.

0x04

Assertion failure. For example, consistency failure.

0x05

Error detected on internal data path. For example, parity on ALU result.

0x06

Data value from associative memory. For example, ECC error on cache data.

0x07

Address/control value from associative memory. For example, ECC error on cache tag.

0x08

Data value from a TLB. For example, ECC error on TLB data.

0x09

Address/control value from a TLB. For example, ECC error on TLB tag.

0x0A

Data value from producer. For example, parity error on write data bus.

0x0B

Address/control value from producer. For example, parity error on address bus.

0x0C

Data value from (non-associative) external memory. For example, ECC error in SDRAM.

0x0D

Illegal address (software fault). For example, access to unpopulated memory.

0x0E

Illegal access (software fault). For example, byte write to word register.

0x0F

Illegal state (software fault). For example, device not ready.

0x10

Internal data register. For example, parity on a SIMD&FP register. For a PE, all general-purpose, stack pointer, SIMD&FP, and SVE registers are data registers.

0x11

Internal control register. For example, Parity on a System register. For a PE, all registers other than general-purpose, stack pointer, SIMD&FP, and SVE registers are control registers.

0x12

Error response from Completer of access. For example, error response from cache write-back.

0x13

External timeout. For example, timeout on interaction with another component.

0x14

Internal timeout. For example, timeout on interface within the component.

0x15

Deferred error from Completer not supported at Requester. For example, poisoned data received from the Completer of an access by a Requester that cannot defer the error further.

0x16

Deferred error from Requester not supported at Completer. For example, poisoned data received from the Requester of an access by a Completer that cannot defer the error further.

0x17

Deferred error from Completer passed through. For example, poisoned data received from the Completer of an access and returned to the Requester.

0x18

Deferred error from Requester passed through. For example, poisoned data received from the Requester of an access and deferred to the Completer.

0x19

Error recorded by PCIe error logs. Indicates that the component has recorded an error in a PCIe error log. This might be the PCIe device status register, AER, DVSEC, or other mechanisms defined by PCIe.

All other values are reserved.

The implemented set of valid values that this field can take is IMPLEMENTATION DEFINED. If any value not in this set is written to this register, then the value read back from this field is UNKNOWN.

Note

This means that one or more bits of this field might be implemented as fixed read-as-zero or read-as-one values.

This field is not valid and reads UNKNOWN if all of the following are true:

  • Any of the following are true:
    • The RAS Common Fault Injection Model Extension is implemented by the node that owns this error record and ERR<q>PFGF.SYN == 0b0.
    • The RAS Common Fault Injection Model Extension is not implemented by the node that owns this error record.
  • ERR<n>STATUS.V == 0b0.

This field ignores writes if ERR<n>STATUS.{CE,DE,UE} != {0b00,0,0}, and the highest priority of these is not being cleared to zero in the same write.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Accessing the ERR<n>STATUS

The {AV, V, UE, ER, OF, MV, CE, DE, PN, UET, CI} fields are write-one-to-clear, meaning writes of zero are ignored, and a write of one or all-ones to the field clears the field to zero. The {IERR, SERR} fields are read/write fields, although the set of implemented valid values is IMPLEMENTATION DEFINED. See also ERR<n>PFGF.SYN.

After reading ERR<n>STATUS, software must clear the valid bits in the register to allow new errors to be recorded. However, between reading the register and clearing the valid bits, a new error might have overwritten the register. To prevent this error being lost by software, the register prevents updates to fields that might have been updated by a new error.

When RAS System Architecture v1.0 is implemented:

  • Writes to the {UE, DE, CE} fields are ignored if the OF bit is set and is not being cleared.
  • Writes to the V bit are ignored if any of the {UE, DE, CE} fields are nonzero and are not being cleared.
  • Writes to the {AV, MV} bits and {ER, PN, UET, IERR, SERR} syndrome fields are ignored if the highest priority error status field is nonzero and not being cleared. The error status fields in priority order from highest to lowest, are UE, DE, and CE.

When RAS System Architecture v1.1 is implemented, a write to the register is ignored if all of:

  • Any of {V, UE, OF, CE, DE} fields are nonzero before the write.
  • The write does not clear the nonzero {V, UE, OF, CE, DE} fields to zero by writing ones to the applicable field or fields.

Some of the fields in ERR<n>STATUS are also defined as UNKNOWN where certain combinations of the {V, DE, UE} status fields are zero. The rules for writes to ERR<n>STATUS allow a node to implement such a field as a fixed read-only value.

For example, when RAS System Architecture v1.1 is implemented, a write to ERR<n>STATUS when ERR<n>STATUS.V is 1 results in either ERR<n>STATUS.V field being cleared to zero, or ERR<n>STATUS.V not changing. Since all fields in ERR<n>STATUS, other than {AV, V, MV}, usually read as UNKNOWN values when ERR<n>STATUS.V is zero, this means those fields can be implemented as read-only if applicable.

To ensure correct and portable operation, when software is clearing the valid bits in the register to allow new errors to be recorded, Arm recommends that software:

  • Determine which fields to clear to zero by reading ERR<n>STATUS.
  • Write ones to all the write-one-to-clear fields that are nonzero.
  • Write zero to all the read/write fields.
  • Write zero to all the write-one-to-clear fields that are zero.

Otherwise, these fields might not have the correct value when a new fault is recorded.

An exception is when the node supports writing to these fields as part of fault injection. See also ERR<n>PFGF.SYN.

ERR<n>STATUS can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
RAS0x010 + (64 * n)ERR<n>STATUS

Accesses on this interface are RW.