GICD_ICENABLER<n>, Interrupt Clear-Enable Registers, n = 0 - 31
The GICD_ICENABLER<n> characteristics are:
Disables forwarding of the corresponding interrupt to the CPU interfaces.
These registers are available in all GIC configurations. If GICD_CTLR.DS==0, these registers are Common.
GICD_ICENABLER0 is Banked for each connected PE with GICR_TYPER.Processor_Number < 8.
Accessing GICD_ICENABLER0 from a PE with GICR_TYPER.Processor_Number > 7 is CONSTRAINED UNPREDICTABLE:
- Register is RAZ/WI.
- An UNKNOWN banked copy of the register is accessed.
GICD_ICENABLER<n> is a 32-bit register.
The GICD_ICENABLER<n> bit assignments are:
Clear_enable_bit<x>, bit [x], for x = 31 to 0
For SPIs and PPIs, controls the forwarding of interrupt number 32n + x to the CPU interfaces. Reads and writes have the following behavior:
If read, indicates that forwarding of the corresponding interrupt is disabled.
If written, has no effect.
If read, indicates that forwarding of the corresponding interrupt is enabled.
If written, disables forwarding of the corresponding interrupt.
After a write of 1 to this bit, a subsequent read of this bit returns 0.
For SGIs, the behavior of this bit is IMPLEMENTATION DEFINED.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
For INTID m, when DIV and MOD are the integer division and modulo operations:
- The corresponding GICD_ICENABLER<n> number, n, is given by n = m DIV 32.
- The offset of the required GICD_ICENABLER is (0x180 + (4*n)).
- The bit number of the required group modifier bit in this register is m MOD 32.
Writing a 1 to a GICD_ICENABLER<n> bit only disables the forwarding of the corresponding interrupt from the Distributor to any CPU interface. It does not prevent the interrupt from changing state, for example becoming pending or active and pending if it is already active.
Accessing the GICD_ICENABLER<n>
For SGIs and PPIs:
- When ARE is 1 for the Security state of an interrupt, the field for that interrupt is RES0 and an implementation is permitted to make the field RAZ/WI in this case.
- Equivalent functionality is provided by GICR_ICENABLER0.
Bits corresponding to unimplemented interrupts are RAZ/WI.
When GICD_CTLR.DS==0, bits corresponding to Group 0 and Secure Group 1 interrupts are RAZ/WI to Non-secure accesses.
Completion of a write to this register does not guarantee that the effects of the write are visible throughout the affinity hierarchy. To ensure an enable has been cleared, software must write to the register with bits set to 1 to clear the required enables. Software must then poll GICD_CTLR.RWP until it has the value zero.
GICD_ICENABLER<n> can be accessed through the memory-mapped interfaces:
|GIC Distributor||0x0180 + (4 * n)||GICD_ICENABLER<n>|
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RW.
- When an access is Secure accesses to this register are RW.
- When an access is Non-secure accesses to this register are RW.