GICD_ICFGR<n>, Interrupt Configuration Registers, n = 0 - 63
The GICD_ICFGR<n> characteristics are:
Purpose
Determines whether the corresponding interrupt is edge-triggered or level-sensitive.
Configuration
These registers are available in all GIC configurations. If the GIC implementation supports two Security states, these registers are Common.
GICD_ICFGR1 is Banked for each connected PE with GICR_TYPER.Processor_Number < 8.
Accessing GICD_ICFGR1 from a PE with GICR_TYPER.Processor_Number > 7 is CONSTRAINED UNPREDICTABLE:
- Register is RAZ/WI.
- An UNKNOWN banked copy of the register is accessed.
For SGIs and PPIs:
- When ARE is 1 for the Security state of an interrupt, the field for that interrupt is RES0 and an implementation is permitted to make the field RAZ/WI in this case.
- Equivalent functionality is provided by GICR_ICFGR<n>
For each supported PPI, it is IMPLEMENTATION DEFINED whether software can program the corresponding Int_config field.
For SGIs, Int_config fields are RO, meaning that GICD_ICFGR0 is RO.
Changing Int_config when the interrupt is individually enabled is UNPREDICTABLE.
Changing the interrupt configuration between level-sensitive and edge-triggered (in either direction) at a time when there is a pending interrupt will leave the interrupt in an UNKNOWN pending state.
Fields corresponding to unimplemented interrupts are RAZ/WI.
Attributes
GICD_ICFGR<n> is a 32-bit register.
Field descriptions
The GICD_ICFGR<n> bit assignments are:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Int_config15 | Int_config14 | Int_config13 | Int_config12 | Int_config11 | Int_config10 | Int_config9 | Int_config8 | Int_config7 | Int_config6 | Int_config5 | Int_config4 | Int_config3 | Int_config2 | Int_config1 | Int_config0 | ||||||||||||||||
Int_config<x>, bits [2x+1:2x], for x = 15 to 0
Indicates whether the interrupt with ID 16n + x is level-sensitive or edge-triggered.
Int_config[0] (bit [2x]) is RES0.
Possible values of Int_config[1] (bit [2x+1]) are:
| Int_config<x> | Meaning |
|---|---|
| 0b00 |
Corresponding interrupt is level-sensitive. |
| 0b01 |
Corresponding interrupt is edge-triggered. |
For SGIs, Int_config[1] is RAO/WI.
For SPIs and PPIs, Int_config[1] is programmable unless the implementation supports two Security states and the bit corresponds to a Group 0 or Secure Group 1 interrupt, in which case the bit is RAZ/WI to Non-secure accesses.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Accessing the GICD_ICFGR<n>
GICD_ICFGR<n> can be accessed through the memory-mapped interfaces:
| Component | Offset | Instance |
|---|---|---|
| GIC Distributor | 0x0C00 + (4 * n) | GICD_ICFGR<n> |
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RW.
- When an access is Secure accesses to this register are RW.
- When an access is Non-secure accesses to this register are RW.