GICD_NSACR<n>E, Non-secure Access Control Registers, n = 0 - 63
The GICD_NSACR<n>E characteristics are:
Enables Secure software to permit Non-secure software on a particular PE to create and control Group 0 interrupts.
This register is present only when FEAT_GICv3p1 is implemented. Otherwise, direct accesses to GICD_NSACR<n>E are RES0.
When GICD_TYPER.ESPI==0, these registers are RES0.
GICD_NSACR<n>E is a 32-bit register.
The GICD_NSACR<n>E bit assignments are:
NS_access<x>, bits [2x+1:2x], for x = 15 to 0
Controls Non-secure access of the interrupt with ID 16n + x.
If the corresponding interrupt does not support configurable Non-secure access, the field is RAZ/WI.
Otherwise, the field is RW and determines the level of Non-secure control permitted if the interrupt is a Secure interrupt. If the interrupt is a Non-secure interrupt, this field is ignored.
The possible values of each 2-bit field are:
No Non-secure access is permitted to fields associated with the corresponding interrupt.
Non-secure read and write access is permitted to set-pending bits in GICD_ISPENDR<n>E associated with the corresponding interrupt. A Non-secure write access to GICD_SETSPI_NSR is permitted to set the pending state of the corresponding interrupt.
As 0b01, but adds Non-secure read and write access permission to fields associated with the corresponding interrupt in the GICD_ICPENDR<n>E registers. A Non-secure write access to GICD_CLRSPI_NSR is permitted to clear the pending state of the corresponding interrupt. Also adds Non-secure read access permission to fields associated with the corresponding interrupt in the GICD_ISACTIVER<n>E and GICD_ICACTIVER<n>E registers.
This encoding is treated as 0b10, but adds Non-secure read and write access permission to GICD_IROUTER<n>E fields associated with the corresponding interrupt.
On a Warm reset, this field resets to 0.
For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
- The corresponding GICD_NSACR<n>E number, n, is given by n = (m - 4096) DIV 16.
- The offset of the required GICD_NSACR<n>E register is (0x3600 + (4*n)).
Accessing the GICD_NSACR<n>E
GICD_NSACR<n>E can be accessed through the memory-mapped interfaces:
|GIC Distributor||0x3600 + (4 * n)||GICD_NSACR<n>E|
This interface is accessible as follows:
- When GICD_CTLR.DS == 1 accesses to this register are RAZ/WI.
- When an access is Secure accesses to this register are RW.
- When an access is Non-secure accesses to this register are RAZ/WI.