GICH_EISR, End Interrupt Status Register
The GICH_EISR characteristics are:
Purpose
Indicates which List registers have outstanding EOI maintenance interrupts.
Configuration
This register is available when the GIC implementation supports interrupt virtualization.
Attributes
GICH_EISR is a 32-bit register.
Field descriptions
The GICH_EISR bit assignments are:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | Status15 | Status14 | Status13 | Status12 | Status11 | Status10 | Status9 | Status8 | Status7 | Status6 | Status5 | Status4 | Status3 | Status2 | Status1 | Status0 | |||||||||||||||
Bits [31:16]
Reserved, RES0.
Status<n>, bit [n], for n = 15 to 0
EOI maintenance interrupt status for List register <n>:
| Status<n> | Meaning |
|---|---|
| 0b0 |
GICH_LR<n> does not have an EOI maintenance interrupt. |
| 0b1 |
GICH_LR<n> has an EOI maintenance interrupt that has not been handled. |
For any GICH_LR<n> register, the corresponding status bit is set to 1 if all of the following are true:
- GICH_LR<n>.State is 0b00.
- GICH_LR<n>.HW == 0.
- GICH_LR<n>.EOI == 1.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Accessing the GICH_EISR
This register is used only when System register access is not enabled. When System register access is enabled:
- For AArch32 implementations, ICH_EISR provides equivalent functionality.
- For AArch64 implementations, ICH_EISR_EL2 provides equivalent functionality.
Bits corresponding to unimplemented List registers are RAZ.
GICH_EISR can be accessed through the memory-mapped interfaces:
| Component | Offset | Instance |
|---|---|---|
| GIC Virtual interface control | 0x0020 | GICH_EISR |
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RO.
- When an access is Secure accesses to this register are RO.
- When an access is Non-secure accesses to this register are RO.