GICH_VMCR, Virtual Machine Control Register
The GICH_VMCR characteristics are:
Purpose
Enables the hypervisor to save and restore the virtual machine view of the GIC state. This register is updated when a virtual machine updates the virtual CPU interface registers.
Configuration
This register is available when the GIC implementation supports interrupt virtualization.
Attributes
GICH_VMCR is a 32-bit register.
Field descriptions
The GICH_VMCR bit assignments are:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VPMR | VBPR0 | VBPR1 | RES0 | VEOIM | RES0 | VCBPR | VFIQEn | VAckCtl | VENG1 | VENG0 | |||||||||||||||||||||
VPMR, bits [31:24]
Virtual priority mask. The priority mask level for the CPU interface. If the priority of an interrupt is higher than the value indicated by this field, the interface signals the interrupt to the PE.
This alias field is updated when a VM updates GICV_PMR.Priority.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
VBPR0, bits [23:21]
Virtual Binary Point Register, Group 0. Defines the point at which the priority value fields split into two parts, the Group priority field and the subpriority field. The Group priority field determines Group 0 interrupt preemption, and also determines Group 1 interrupt preemption if GICH_VMCR.VCBPR == 1.
This alias field is updated when a VM updates GICV_BPR.Binary_Point.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
VBPR1, bits [20:18]
Virtual Binary Point Register, Group 1. Defines the point at which the priority value fields split into two parts, the Group priority field and the subpriority field. The Group priority field determines Group 1 interrupt preemption if GICH_VMCR.VCBPR == 0.
This alias field is updated when a VM updates GICV_ABPR.Binary_Point.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Bits [17:10]
Reserved, RES0.
VEOIM, bit [9]
Virtual EOImode. Possible values of this bit are:
| VEOIM | Meaning |
|---|---|
| 0b0 |
A write of an INTID to GICV_EOIR or GICV_AEOIR drops the priority of the interrupt with that INTID, and also deactivates that interrupt. |
| 0b1 |
A write of an INTID to GICV_EOIR or GICV_AEOIR only drops the priority of the interrupt with that INTID. Software must write to GICV_DIR to deactivate the interrupt. |
This alias field is updated when a VM updates GICV_CTLR.EOImode.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Bits [8:5]
Reserved, RES0.
VCBPR, bit [4]
Virtual Common Binary Point Register. Possible values of this bit are:
| VCBPR | Meaning |
|---|---|
| 0b0 |
GICV_ABPR determines the preemption group for Group 1 interrupts. |
| 0b1 |
GICV_BPR determines the preemption group for Group 1 interrupts. |
This alias field is updated when a VM updates GICV_CTLR.CBPR.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
VFIQEn, bit [3]
Virtual FIQ enable. Possible values of this bit are:
| VFIQEn | Meaning |
|---|---|
| 0b0 |
Group 0 virtual interrupts are presented as virtual IRQs. |
| 0b1 |
Group 0 virtual interrupts are presented as virtual FIQs. |
This alias field is updated when a VM updates GICV_CTLR.FIQEn.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
VAckCtl, bit [2]
Virtual AckCtl. Possible values of this bit are:
| VAckCtl | Meaning |
|---|---|
| 0b0 |
If the highest priority pending interrupt is Group 1, a read of GICV_IAR or GICV_HPPIR returns an INTID of 1022. |
| 0b1 |
If the highest priority pending interrupt is Group 1, a read of GICV_IAR or GICV_HPPIR returns the INTID of the corresponding interrupt. |
This alias field is updated when a VM updates GICV_CTLR.AckCtl.
This field is supported for backwards compatibility with GICv2. Arm deprecates the use of this field.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
VENG1, bit [1]
Virtual interrupt enable, Group 1. Possible values of this bit are:
| VENG1 | Meaning |
|---|---|
| 0b0 |
Group 1 virtual interrupts are disabled. |
| 0b1 |
Group 1 virtual interrupts are enabled. |
This alias field is updated when a VM updates GICV_CTLR.EnableGrp1.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
VENG0, bit [0]
Virtual interrupt enable, Group 0. Possible values of this bit are:
| VENG0 | Meaning |
|---|---|
| 0b0 |
Group 0 virtual interrupts are disabled. |
| 0b1 |
Group 0 virtual interrupts are enabled. |
This alias field is updated when a VM updates GICV_CTLR.EnableGrp0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
A List register is in the pending state only if the corresponding GICH_LR<n> value is 0b01, that is, pending. The active and pending state is not included.
Accessing the GICH_VMCR
This register is used only when System register access is not enabled. When System register access is enabled:
- For AArch32 implementations, ICH_VMCR provides equivalent functionality.
- For AArch64 implementations, ICH_VMCR_EL2 provides equivalent functionality.
GICH_VMCR can be accessed through the memory-mapped interfaces:
| Component | Offset | Instance |
|---|---|---|
| GIC Virtual interface control | 0x0008 | GICH_VMCR |
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RW.
- When an access is Secure accesses to this register are RW.
- When an access is Non-secure accesses to this register are RW.