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GICR_ICFGR<n>E, Interrupt configuration registers, n = 2 - 5

The GICR_ICFGR<n>E characteristics are:


Determines whether the corresponding PPI in the extended PPI range is edge-triggered or level-sensitive.


This register is present only when FEAT_GICv3p1 is implemented. Otherwise, direct accesses to GICR_ICFGR<n>E are RES0.

A copy of this register is provided for each Redistributor.


GICR_ICFGR<n>E is a 32-bit register.

Field descriptions

The GICR_ICFGR<n>E bit assignments are:

Int_config<x>, bit [x], for x = 31 to 0

Indicates whether the interrupt with ID 16n + x is level-sensitive or edge-triggered.

Int_config[0] (bit [2x]) is RES0.

Possible values of Int_config[1] (bit [2x+1]) are:


The corresponding interrupt is level-sensitive.


The corresponding interrupt is edge-triggered.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

For each supported extended PPI, it is IMPLEMENTATION DEFINED whether software can program the corresponding Int_config field.

Accessing the GICR_ICFGR<n>E

When affinity routing is not enabled for the Security state of an interrupt in GICR_ICFGR<n>E, the corresponding bit is RES0.

When GICD_CTLR.DS==0, a register bit that corresponds to a Group 0 or Secure Group 1 interrupt is RAZ/WI to Non-secure accesses.

Bits corresponding to unimplemented interrupts are RAZ/WI.

GICR_ICFGR<n>E can be accessed through the memory-mapped interfaces:

GIC RedistributorSGI_base0x0C00 + (4 * n)GICR_ICFGR<n>E

This interface is accessible as follows:

  • When GICD_CTLR.DS == 0 accesses to this register are RW.
  • When an access is Secure accesses to this register are RW.
  • When an access is Non-secure accesses to this register are RW.