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GICR_ICPENDR<n>E, Interrupt Clear-Pending Registers, n = 1 - 2

The GICR_ICPENDR<n>E characteristics are:

Purpose

Removes the pending state from the corresponding PPI.

Configuration

This register is present only when FEAT_GICv3p1 is implemented. Otherwise, direct accesses to GICR_ICPENDR<n>E are RES0.

A copy of this register is provided for each Redistributor.

Attributes

GICR_ICPENDR<n>E is a 32-bit register.

Field descriptions

The GICR_ICPENDR<n>E bit assignments are:

313029282726252423222120191817161514131211109876543210
Clear_pending_bit31Clear_pending_bit30Clear_pending_bit29Clear_pending_bit28Clear_pending_bit27Clear_pending_bit26Clear_pending_bit25Clear_pending_bit24Clear_pending_bit23Clear_pending_bit22Clear_pending_bit21Clear_pending_bit20Clear_pending_bit19Clear_pending_bit18Clear_pending_bit17Clear_pending_bit16Clear_pending_bit15Clear_pending_bit14Clear_pending_bit13Clear_pending_bit12Clear_pending_bit11Clear_pending_bit10Clear_pending_bit9Clear_pending_bit8Clear_pending_bit7Clear_pending_bit6Clear_pending_bit5Clear_pending_bit4Clear_pending_bit3Clear_pending_bit2Clear_pending_bit1Clear_pending_bit0

Clear_pending_bit<x>, bit [x], for x = 31 to 0

For the extended PPIs, removes the pending state to interrupt number x. Reads and writes have the following behavior:

Clear_pending_bit<x>Meaning
0b0

If read, indicates that the corresponding interrupt is not pending on this PE.

If written, has no effect.

0b1

If read, indicates that the corresponding interrupt is pending, or active and pending on this PE.

If written, changes the state of the corresponding interrupt from pending to inactive, or from active and pending to active.

This has no effect in the following cases:

  • If the interrupt is not pending and is not active and pending.

  • If the interrupt is a level-sensitive interrupt that is pending or active and pending for a reason other than a write to GICR_ISPENDR<n>E. In this case, if the interrupt signal continues to be asserted, the interrupt remains pending or active and pending.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

For INTID m, when DIV and MOD are the integer division and modulo operations:

  • The corresponding GICR_ICPENDR<n>E number, n, is given by n = (m-1024) DIV 32.
  • The offset of the required GICR_ICPENDR<n>E is (0x200 + (4*n)).
  • The bit number of the required group modifier bit in this register is (m-1024) MOD 32.

Accessing the GICR_ICPENDR<n>E

When affinity routing is not enabled for the Security state of an interrupt in GICR_ICPENDR<n>E, the corresponding bit is RES0.

When GICD_CTLR.DS==0, bits corresponding to Secure PPIs are RAZ/WI to Non-secure accesses.

Bits corresponding to unimplemented interrupts are RAZ/WI.

GICR_ICPENDR<n>E can be accessed through the memory-mapped interfaces:

ComponentFrameOffsetInstance
GIC RedistributorSGI_base0x0280 + (4 * n)GICR_ICPENDR<n>E

This interface is accessible as follows:

  • When GICD_CTLR.DS == 0 accesses to this register are RW.
  • When an access is Secure accesses to this register are RW.
  • When an access is Non-secure accesses to this register are RW.


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