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GICR_ISPENDR<n>E, Interrupt Set-Pending Registers, n = 1 - 2

The GICR_ISPENDR<n>E characteristics are:

Purpose

Adds the pending state to the corresponding PPI.

Configuration

This register is present only when FEAT_GICv3p1 is implemented. Otherwise, direct accesses to GICR_ISPENDR<n>E are RES0.

A copy of this register is provided for each Redistributor.

Attributes

GICR_ISPENDR<n>E is a 32-bit register.

Field descriptions

The GICR_ISPENDR<n>E bit assignments are:

313029282726252423222120191817161514131211109876543210
Set_pending_bit31Set_pending_bit30Set_pending_bit29Set_pending_bit28Set_pending_bit27Set_pending_bit26Set_pending_bit25Set_pending_bit24Set_pending_bit23Set_pending_bit22Set_pending_bit21Set_pending_bit20Set_pending_bit19Set_pending_bit18Set_pending_bit17Set_pending_bit16Set_pending_bit15Set_pending_bit14Set_pending_bit13Set_pending_bit12Set_pending_bit11Set_pending_bit10Set_pending_bit9Set_pending_bit8Set_pending_bit7Set_pending_bit6Set_pending_bit5Set_pending_bit4Set_pending_bit3Set_pending_bit2Set_pending_bit1Set_pending_bit0

Set_pending_bit<x>, bit [x], for x = 31 to 0

For the extended PPIs, adds the pending state to interrupt number x. Reads and writes have the following behavior:

Set_pending_bit<x>Meaning
0b0

If read, indicates that the corresponding interrupt is not pending on this PE.

If written, has no effect.

0b1

If read, indicates that the corresponding interrupt is pending, or active and pending on this PE.

If written, changes the state of the corresponding interrupt from inactive to pending, or from active to active and pending.

This has no effect in the following cases:

  • If the interrupt is already pending because of a write to GICR_ISPENDR<n>E.

  • If the interrupt is already pending because the corresponding interrupt signal is asserted. In this case, the interrupt remains pending if the interrupt signal is deasserted.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

For INTID m, when DIV and MOD are the integer division and modulo operations:

  • The corresponding GICR_ISPENDR<n>E number, n, is given by n = (m-1024) DIV 32.
  • The offset of the required GICR_ISPENDR<n>E is (0x200 + (4*n)).
  • The bit number of the required group modifier bit in this register is (m-1024) MOD 32.

Accessing the GICR_ISPENDR<n>E

When affinity routing is not enabled for the Security state of an interrupt in GICR_ISPENDR<n>E, the corresponding bit is RES0.

When GICD_CTLR.DS==0, bits corresponding to Secure PPIs are RAZ/WI to Non-secure accesses.

Bits corresponding to unimplemented interrupts are RAZ/WI.

GICR_ISPENDR<n>E can be accessed through the memory-mapped interfaces:

ComponentFrameOffsetInstance
GIC RedistributorSGI_base0x0200 + (4 * n)GICR_ISPENDR<n>E

This interface is accessible as follows:

  • When GICD_CTLR.DS == 0 accesses to this register are RW.
  • When an access is Secure accesses to this register are RW.
  • When an access is Non-secure accesses to this register are RW.


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