GICR_PENDBASER, Redistributor LPI Pending Table Base Address Register
The GICR_PENDBASER characteristics are:
Purpose
Specifies the base address of the LPI Pending table, and the Shareability and Cacheability of accesses to the LPI Pending table.
Configuration
A copy of this register is provided for each Redistributor.
Attributes
GICR_PENDBASER is a 64-bit register.
Field descriptions
The GICR_PENDBASER bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| RES0 | PTZ | RES0 | OuterCache | RES0 | Physical_Address | ||||||||||||||||||||||||||
| Physical_Address | RES0 | Shareability | InnerCache | RES0 | |||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bit [63]
Reserved, RES0.
PTZ, bit [62]
Pending Table Zero. Indicates to the Redistributor whether the LPI Pending table is zero when GICR_CTLR.EnableLPIs == 1.
This field is WO, and reads as 0.
| PTZ | Meaning |
|---|---|
| 0b0 |
The LPI Pending table is not zero, and contains live data. |
| 0b1 |
The LPI Pending table is zero. Software must ensure the LPI Pending table is zero before this value is written. |
Bits [61:59]
Reserved, RES0.
OuterCache, bits [58:56]
Indicates the Outer Cacheability attributes of accesses to the LPI Pending table. The possible values of this field are:
| OuterCache | Meaning |
|---|---|
| 0b000 |
Memory type defined in InnerCache field. For Normal memory, Outer Cacheability is the same as Inner Cacheability. |
| 0b001 |
Normal Outer Non-cacheable. |
| 0b010 |
Normal Outer Cacheable Read-allocate, Write-through. |
| 0b011 |
Normal Outer Cacheable Read-allocate, Write-back. |
| 0b100 |
Normal Outer Cacheable Write-allocate, Write-through. |
| 0b101 |
Normal Outer Cacheable Write-allocate, Write-back. |
| 0b110 |
Normal Outer Cacheable Read-allocate, Write-allocate, Write-through. |
| 0b111 |
Normal Outer Cacheable Read-allocate, Write-allocate, Write-back. |
It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Bits [55:52]
Reserved, RES0.
Physical_Address, bits [51:16]
Bits [51:16] of the physical address containing the LPI Pending table.
In implementations supporting fewer than 52 bits of physical address, unimplemented upper bits are RES0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Bits [15:12]
Reserved, RES0.
Shareability, bits [11:10]
Indicates the Shareability attributes of accesses to the LPI Pending table. The possible values of this field are:
| Shareability | Meaning |
|---|---|
| 0b00 |
Non-shareable. |
| 0b01 |
Inner Shareable. |
| 0b10 |
Outer Shareable. |
| 0b11 |
Reserved. Treated as 0b00. |
It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
InnerCache, bits [9:7]
Indicates the Inner Cacheability attributes of accesses to the LPI Pending table. The possible values of this field are:
| InnerCache | Meaning |
|---|---|
| 0b000 |
Device-nGnRnE. |
| 0b001 |
Normal Inner Non-cacheable. |
| 0b010 |
Normal Inner Cacheable Read-allocate, Write-through. |
| 0b011 |
Normal Inner Cacheable Read-allocate, Write-back. |
| 0b100 |
Normal Inner Cacheable Write-allocate, Write-through. |
| 0b101 |
Normal Inner Cacheable Write-allocate, Write-back. |
| 0b110 |
Normal Inner Cacheable Read-allocate, Write-allocate, Write-through. |
| 0b111 |
Normal Inner Cacheable Read-allocate, Write-allocate, Write-back. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Bits [6:0]
Reserved, RES0.
Accessing the GICR_PENDBASER
Having the GICR_PENDBASER OuterCache, Shareability or InnerCache fields programmed to different values on different Redistributors with GICR_CTLR.EnableLPIs == 1 in the system is UNPREDICTABLE.
Changing GICR_PENDBASER with GICR_CTLR.EnableLPIs == 1 is UNPREDICTABLE.
GICR_PENDBASER can be accessed through the memory-mapped interfaces:
| Component | Frame | Offset | Instance |
|---|---|---|---|
| GIC Redistributor | RD_base | 0x0078 | GICR_PENDBASER |
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RW.
- When an access is Secure accesses to this register are RW.
- When an access is Non-secure accesses to this register are RW.