GICR_SYNCR, Redistributor Synchronize Register
The GICR_SYNCR characteristics are:
Indicates completion of register based invalidate operations.
A copy of this register is provided for each Redistributor.
GICR_SYNCR is a 32-bit register.
The GICR_SYNCR bit assignments are:
Busy, bit 
Indicates completion of invalidation operations
No operations are in progress.
A write is in progress to one or more of the following registers:
This field tracks operations initiated on the same Redistributor.
Accessing the GICR_SYNCR
When this register is accessed, it is optional that an implementation might wait until all operations are complete before returning a value, in which case GICR_SYNCR.Busy is always 0.
This register is mandatory when any of the following are true:
Otherwise, the functionality is IMPLEMENTATION DEFINED.
GICR_SYNCR can be accessed through the memory-mapped interfaces:
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RO.
- When an access is Secure accesses to this register are RO.
- When an access is Non-secure accesses to this register are RO.