GICR_VPENDBASER, Virtual Redistributor LPI Pending Table Base Address Register
The GICR_VPENDBASER characteristics are:
Purpose
Specifies the base address of the memory that holds the virtual LPI Pending table for the currently scheduled virtual machine.
Configuration
Attributes
GICR_VPENDBASER is a 64-bit register.
Field descriptions
The GICR_VPENDBASER bit assignments are:
When FEAT_GICv4 is implemented:63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Valid IDAI PendingLast Dirty RES0 OuterCache RES0 Physical_Address Physical_Address RES0 Shareability InnerCache RES0
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| Valid | IDAI | PendingLast | Dirty | RES0 | OuterCache | RES0 | Physical_Address | ||||||||||||||||||||||||
| Physical_Address | RES0 | Shareability | InnerCache | RES0 | |||||||||||||||||||||||||||
Valid, bit [63]
This bit controls whether the virtual LPI Pending table is valid.
| Valid | Meaning |
|---|---|
| 0b0 |
The virtual LPI Pending table is not valid. No vPE is scheduled. |
| 0b1 |
The virtual LPI Pending table is valid. A vPE is scheduled. |
Setting GICR_VPENDBASER.Valid == 1 when the associated CPU interface does not implement FEAT_GICv4 is UNPREDICTABLE.
Software can determine whether a PE supports FEAT_GICv3 or FEAT_GICv4 by reading ID_AA64PFR0_EL1.
Writing a new value to any bit of GICR_VPENDBASER, other than GICR_VPENDBASER.Valid, when GICR_VPENDBASER.Valid==1 is UNPREDICTABLE.
On a Warm reset, this field resets to 0.
IDAI, bit [62]
Implementation Defined Area Invalid. Indicates whether the IMPLEMENTATION DEFINED area in the virtual LPI Pending table is valid.
| IDAI | Meaning |
|---|---|
| 0b0 |
The IMPLEMENTATION DEFINED area is valid. |
| 0b1 |
The IMPLEMENTATION DEFINED area is invalid and all pending interrupt information is held in the architecturally defined part of the virtual LPI Pending table. |
For more information, see 'LPI Pending tables' and 'Virtual LPI Configuration tables and virtual LPI Pending tables' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).
On a Warm reset, this field resets to an architecturally UNKNOWN value.
PendingLast, bit [61]
Indicates whether there are pending and enabled interrupts for the last scheduled vPE.
This value is set by the implementation when GICR_VPENDBASER.Valid has been written from 1 to 0 and is otherwise UNKNOWN.
| PendingLast | Meaning |
|---|---|
| 0b0 |
There are no pending and enabled interrupts for the last scheduled vPE. |
| 0b1 | There is at least one pending interrupt for the last scheduled vPE. It is IMPLEMENTATION DEFINED whether this bit is set when the only pending interrupts for the last scheduled vPE are not enabled. Arm deprecates setting PendingLast to 1 when the only pending interrupts for the last scheduled virtual machine are not enabled. |
When the GICR_VPENDBASER.Valid bit is written from 0 to 1, this bit is RES1.
On a Warm reset, this field resets to 0.
Dirty, bit [60]
When GICR_VPENDBASER.Valid == 0:
When GICR_VPENDBASER.Valid == 0:
Indicates whether a de-scheduling operation is in progress.
This field is read-only.
| Dirty | Meaning |
|---|---|
| 0b0 |
No de-scheduling operation in process. |
| 0b1 |
De-scheduling operation in process. |
Writing 1 to GICR_VPENDBASER.Valid is UNPREDICTABLE while GICR_VPENDBASER.Dirty==1.
On a Warm reset, this field resets to 0.
When GICR_VPENDBASER.Valid == 1 and GICR_TYPER.Dirty == 1:
When GICR_VPENDBASER.Valid == 1 and GICR_TYPER.Dirty == 1:
This field is read-only. Reports whether the Virtual Pending table has been parsed.
| Dirty | Meaning |
|---|---|
| 0b0 |
Parsing of the Virtual Pending Table has completed. |
| 0b1 |
Parsing of the Virtual Pending Table has not completed. |
Writing 1 to GICR_VPENDBASER.Valid is UNPREDICTABLE while GICR_VPENDBASER.Dirty == 1.
On a Warm reset, this field resets to 0.
Otherwise:
Otherwise:
This field is read-only. This fields is UNKNOWN.
On a Warm reset, this field resets to 0.
Bit [59]
Reserved, RES0.
OuterCache, bits [58:56]
Indicates the Outer Cacheability attributes of accesses to virtual LPI Pending tables of vPEs targeting this Redistributor.
| OuterCache | Meaning |
|---|---|
| 0b000 |
Memory type defined in InnerCache field. For Normal memory, Outer Cacheability is the same as Inner Cacheability. |
| 0b001 |
Normal Outer Non-cacheable. |
| 0b010 |
Normal Outer Cacheable Read-allocate, Write-through. |
| 0b011 |
Normal Outer Cacheable Read-allocate, Write-back. |
| 0b100 |
Normal Outer Cacheable Write-allocate, Write-through. |
| 0b101 |
Normal Outer Cacheable Write-allocate, Write-back. |
| 0b110 |
Normal Outer Cacheable Read-allocate, Write-allocate, Write-through. |
| 0b111 |
Normal Outer Cacheable Read-allocate, Write-allocate, Write-back. |
It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated.
The Cacheability, Outer Cacheability and Shareability fields are used for accesses to the virtual LPI Pending table of resident and non-resident vPEs.
If the OuterCacheabilty attribute of the virtual LPI Pending tables that are associated with vPEs targeting the same Redistributor are different, behavior is UNPREDICTABLE.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Bits [55:52]
Reserved, RES0.
Physical_Address, bits [51:16]
Bits [51:16] of the physical address containing the virtual LPI Pending table.
In implementations supporting fewer than 52 bits of physical address, unimplemented upper bits are RES0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Bits [15:12]
Reserved, RES0.
Shareability, bits [11:10]
Indicates the Shareability attributes of accesses to the virtual LPI Pending table.
| Shareability | Meaning |
|---|---|
| 0b00 |
Non-shareable. |
| 0b01 |
Inner Shareable. |
| 0b10 |
Outer Shareable. |
| 0b11 |
Reserved. Treated as 0b00. |
It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated.
The Cacheability, Outer Cacheability and Shareability fields are used for accesses to the virtual LPI Pending table of resident and non-resident vPEs.
If the Shareability attribute of the virtual LPI Pending tables that are associated with vPEs targeting the same Redistributor are different, behavior is UNPREDICTABLE.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
InnerCache, bits [9:7]
Indicates the Inner Cacheability attributes of accesses to the virtual LPI Pending table.
| InnerCache | Meaning |
|---|---|
| 0b000 |
Device-nGnRnE. |
| 0b001 |
Normal Inner Non-cacheable. |
| 0b010 |
Normal Inner Cacheable Read-allocate, Write-through. |
| 0b011 |
Normal Inner Cacheable Read-allocate, Write-back. |
| 0b100 |
Normal Inner Cacheable Write-allocate, Write-through. |
| 0b101 |
Normal Inner Cacheable Write-allocate, Write-back. |
| 0b110 |
Normal Inner Cacheable Read-allocate, Write-allocate, Write-through. |
| 0b111 |
Normal Inner Cacheable Read-allocate, Write-allocate, Write-back. |
The Cacheability, Outer Cacheability and Shareability fields are used for accesses to the virtual LPI Pending table of resident and non-resident vPEs.
If the InnerCacheabilty attribute of the virtual LPI Pending tables that are associated with vPEs targeting the same Redistributor are different, behavior is UNPREDICTABLE.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Bits [6:0]
Reserved, RES0.
When FEAT_GICv4p1 is implemented:
Valid, bit [63]
This bit controls whether a vPE is scheduled:
| Valid | Meaning |
|---|---|
| 0b0 |
The virtual LPI Pending table is not valid. No vPE is scheduled. |
| 0b1 |
The virtual LPI Pending table is valid. A vPE is scheduled. |
Setting GICR_VPENDBASER.Valid == 1 when the associated CPU interface does not implement FEAT_GICv4 is UNPREDICTABLE.
Software can determine whether a PE supports FEAT_GICv3 or FEAT_GICv4 by reading ID_AA64PFR0_EL1.
Writing a new value to any bit of GICR_VPENDBASER, other than GICR_VPENDBASER.Valid, when GICR_VPENDBASER.Valid==1 is UNPREDICTABLE.
Setting GICR_VPENDBASER.Valid to 1 is UNPREDICTABLE if GICR_VPROPBASER.Valid == 0.
On a Warm reset, this field resets to 0.
Doorbell, bit [62]
When GICR_VPENDBASER.Valid is written from 1 to 0, this bit controls whether a default doorbell interrupt is requested for the descheduled vPE.
| Doorbell | Meaning |
|---|---|
| 0b0 |
No default doorbell requested. |
| 0b1 |
Default doorbell requested. |
When GICR_VPENDBASER.Valid is written from 1 to 0, if there are outstanding enabled pending interrupts then this bit is treated as 0.
When GICR_VPENDBASER.Valid is written from 1 to 0, if GICR_VPENDBASER.PendingLast is written as 1 then this bit is treated as 0.
When GICR_VPENDBASER.Valid == 1, reads return an UNKNOWN value.
On a Warm reset, this field resets to an UNKNOWN value.
PendingLast, bit [61]
Indicates whether there are pending and enabled interrupts for the last scheduled vPE.
This value is set by the implementation when GICR_VPENDBASER.Valid is written from 1 to 0 and is otherwise UNKNOWN.
| PendingLast | Meaning |
|---|---|
| 0b0 |
There are no pending and enabled interrupts for the last scheduled vPE. |
| 0b1 |
There is at least one pending and enabled interrupt for the last scheduled vPE. |
When the GICR_VPENDBASER.Valid bit is written from 0 to 1, this bit is RES1.
When GICR_VPENDBASER.Valid is written from 1 to 0, if GICR_VPENDBASER.PendingLast is written as 1, then this bit is set to an UNKNOWN value.
On a Warm reset, this field resets to an UNKNOWN value.
Dirty, bit [60]
When GICR_VPENDBASER.Valid == 0:
When GICR_VPENDBASER.Valid == 0:
Read-only. Indicates whether a de-scheduling operation is in progress.
| Dirty | Meaning |
|---|---|
| 0b0 |
No de-scheduling operation in progess. |
| 0b1 |
De-scheduling operation in progess. |
Writing 1 to GICR_VPENDBASER.Valid is UNPREDICTABLE while GICR_VPENDBASER.Dirty == 1.
On a Warm reset, this field resets to 0.
Otherwise:
Otherwise:
Read-only. Reports whether the Virtual Pending table has been parsed.
| Dirty | Meaning |
|---|---|
| 0b0 |
Parsing of the Virtual Pending Table is complete. |
| 0b1 |
Parsing of the Virtual Pending Table has not completed. |
Writing 1 to GICR_VPENDBASER.Valid is UNPREDICTABLE while GICR_VPENDBASER.Dirty == 1.
On a Warm reset, this field resets to 0.
VGrp0En, bit [59]
Enable virtual Group 0 interrupts.
| VGrp0En | Meaning |
|---|---|
| 0b0 |
Forwarding of virtual Group 0 interrupts disabled. |
| 0b1 |
Forwarding of virtual Group 0 interrupts enabled. |
Writing a new value to VGrp0En while GICR_VPENDBASER.Valid==1 is CONSTRAINED UNPREDICTABLE:
-
The update is ignored.
-
The update is ignored for all purposes other than a direct read of the register.
-
The virtual group enable is updated.
On a Warm reset, this field resets to an UNKNOWN value.
VGrp1En, bit [58]
Enable virtual Group 1 interrupts.
| VGrp1En | Meaning |
|---|---|
| 0b0 |
Forwarding of virtual Group 1 interrupts disabled. |
| 0b1 |
Forwarding of virtual Group 1 interrupts enabled. |
Writing a new value to VGrp1En while GICR_VPENDBASER.Valid==1 is CONSTRAINED UNPREDICTABLE:
-
The update is ignored.
-
The update is ignored for all purposes other than a direct read of the register.
-
The virtual group enable is updated.
On a Warm reset, this field resets to an UNKNOWN value.
Bits [57:16]
Reserved, RES0.
vPEID, bits [15:0]
When GICR_VPENDBASER.Valid == 1, ID of scheduled vPE.
When GICR_VPENDBASER.Valid == 1, if GICR_VPENDBASER.vPEID is set to a value greater than the configured vPEID width, the behavior of this field is CONSTRAINED UNPREDICTABLE:
-
GICR_VPENDBASER.vPEID is treated as having an UNKNOWN valid value for all purposes other than a direct read of the register.
-
GICR_VPENDBASER.Valid is treated as being set to 0 for all purposes other than a direct read of the register.
The size of this field is IMPLEMENTATION DEFINED, and is specified by the GICD_TYPER2.VIL and GICD_TYPER2.VID fields, unimplemented bits are RES0.
Accessing the GICR_VPENDBASER
The effect of a write to this register is not guaranteed to be visible throughout the affinity hierarchy, as indicated by GICR_CTLR.RWP == 0.
GICR_VPENDBASER can be accessed through the memory-mapped interfaces:
| Component | Frame | Offset | Instance |
|---|---|---|---|
| GIC Redistributor | VLPI_base | 0x0078 | GICR_VPENDBASER |
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RW.
- When an access is Secure accesses to this register are RW.
- When an access is Non-secure accesses to this register are RW.