GICV_ABPR, Virtual Machine Aliased Binary Point Register
The GICV_ABPR characteristics are:
Defines the point at which the priority value fields split into two parts, the group priority field and the subpriority field. The group priority field determines Group 1 interrupt preemption.
This register corresponds to GICC_ABPR in the physical CPU interface.
GICH_LR<n>.Group determines whether a virtual interrupt is Group 0 or Group 1.
This register is available when the GIC implementation supports interrupt virtualization.
GICV_ABPR is a 32-bit register.
The GICV_ABPR bit assignments are:
Binary_Point, bits [2:0]
Controls how the 8-bit interrupt priority field is split into a group priority field, that determines interrupt preemption, and a subpriority field.
For information about how this field determines the interrupt priority bits assigned to the group priority field, see 'Priority grouping' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).
On a Warm reset, this field resets to 0.
The Binary_Point field of this register is aliased to GICH_VMCR.VBPR1.
Accessing the GICV_ABPR
This register is used only when System register access is not enabled. When System register access is enabled:
- For AArch32 implementations, ICC_BPR1 provides equivalent functionality.
- For AArch64 implementations, ICC_BPR1_EL1 provides equivalent functionality.
The value contained in this register is one greater than the actual applied binary point value, as described in 'Priority grouping' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).
GICV_ABPR can be accessed through the memory-mapped interfaces:
|GIC Virtual CPU interface||0x001C||GICV_ABPR|
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RW.
- When an access is Secure accesses to this register are RW.
- When an access is Non-secure accesses to this register are RW.