GICV_HPPIR, Virtual Machine Highest Priority Pending Interrupt Register
The GICV_HPPIR characteristics are:
Purpose
Provides the INTID of the highest priority pending Group 0 virtual interrupt in the List registers.
This register corresponds to the physical CPU interface register GICC_HPPIR.
Configuration
This register is available when the GIC implementation supports interrupt virtualization.
Attributes
GICV_HPPIR is a 32-bit register.
Field descriptions
The GICV_HPPIR bit assignments are:
Bits [31:25]
Reserved, RES0.
INTID, bits [24:0]
The INTID of the signaled interrupt.
INTIDs 1020-1023 are reserved and convey additional information such as spurious interrupts.
When affinity routing is not enabled:
- Bits [23:13] are RES0.
- For SGIs, bits [12:10] identify the CPU interface corresponding to the source PE. For all other interrupts these bits are RES0.
Reads of the GICC_HPPIR that do not return a valid INTID return a spurious INTID, 1022 or 1023. See 'Special INTIDs' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).
| Highest priority pending interrupt Group | GICV_HPPIR read | GICV_CTLR.AckCtl | Returned INTID |
|---|---|---|---|
| 1 | Non-secure | x | ID of Group 1 interrupt |
| 1 | Secure | 0 | 1022 |
| 1 | Secure | 1 | ID of Group 1 interrupt |
| 0 | Non-secure | x | 1023 |
| 0 | Secure | x | ID of Group 0 interrupt |
| No pending interrupts | x | x | 1023 |
If the CPU interface supports only a single Security state, the entries that apply to Secure reads describe the behavior.
Accessing the GICV_HPPIR
This register is used only when System register access is not enabled. When System register access is enabled:
- For AArch32 implementations, ICC_HPPIR0 provides equivalent functionality.
- For AArch64 implementations, ICC_HPPIR0_EL1 provides equivalent functionality.
This register is used for Group 0 interrupts only. GICV_AHPPIR provides equivalent functionality for Group 1 interrupts.
When affinity routing is enabled, it is a programming error to use memory-mapped registers to access the GIC.
GICV_HPPIR can be accessed through the memory-mapped interfaces:
| Component | Offset | Instance |
|---|---|---|
| GIC Virtual CPU interface | 0x0018 | GICV_HPPIR |
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RO.
- When an access is Secure accesses to this register are RO.
- When an access is Non-secure accesses to this register are RO.