MPAMF_SIDR, MPAM Features Secure Identification Register
The MPAMF_SIDR characteristics are:
Purpose
The MPAMF_SIDR is a 32-bit read-only register that indicates the maximum Secure PARTID and Secure PMG on this MSC.
Configuration
The power domain of MPAMF_SIDR is IMPLEMENTATION DEFINED.
This register is present only when FEAT_MPAM is implemented. Otherwise, direct accesses to MPAMF_SIDR are RES0.
Attributes
MPAMF_SIDR is a 32-bit register.
Field descriptions
The MPAMF_SIDR bit assignments are:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | S_PMG_MAX | S_PARTID_MAX | |||||||||||||||||||||||||||||
Bits [31:24]
Reserved, RES0.
S_PMG_MAX, bits [23:16]
Maximum value of Secure PMG supported by this component.
S_PARTID_MAX, bits [15:0]
Maximum value of Secure PARTID supported by this component.
Accessing the MPAMF_SIDR
This register is only within the Secure MPAM feature page memory frame.
MPAMF_SIDR is read-only.
MPAMF_SIDR must only be readable from the Secure MPAM feature page. If the system or the MSC does not support the Secure address map, this register must not be accessible.
MPAMF_SIDR can be accessed through the memory-mapped interfaces:
| Component | Frame | Offset | Instance |
|---|---|---|---|
| MPAM | MPAMF_BASE_s | 0x0008 | MPAMF_SIDR_s |
Accesses on this interface are RO.