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PMDEVAFF0, Performance Monitors Device Affinity register 0
The PMDEVAFF0 characteristics are:
Purpose
Copy of the low half of the PE MPIDR_EL1 register that allows a debugger to determine which PE in a multiprocessor system the Performance Monitor component relates to.
Configuration
If FEAT_DoPD is implemented, this register is in the Core power domain. If FEAT_DoPD is not implemented, this register is in the Debug power domain.
This register is required if the external interface to the PMU is implemented.
Attributes
PMDEVAFF0 is a 32-bit register.
Field descriptions
The PMDEVAFF0 bit assignments are:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MPIDR_EL1lo | |||||||||||||||||||||||||||||||
MPIDR_EL1lo, bits [31:0]
MPIDR_EL1 low half. Read-only copy of the low half of MPIDR_EL1, as seen from the highest implemented Exception level.
Accessing the PMDEVAFF0
PMDEVAFF0 can be accessed through the external debug interface:
| Component | Offset | Instance |
|---|---|---|
| PMU | 0xFA8 | PMDEVAFF0 |
This interface is accessible as follows:
- When FEAT_DoPD is not implemented or IsCorePowered() accesses to this register are RO.
- Otherwise accesses to this register generate an error response.