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PMPIDR1, Performance Monitors Peripheral Identification Register 1

The PMPIDR1 characteristics are:


Provides information to identify a Performance Monitor component.

For more information, see 'About the Peripheral identification scheme'.


Implementation of this register is OPTIONAL.

If FEAT_DoPD is implemented, this register is in the Core power domain. If FEAT_DoPD is not implemented, this register is in the Debug power domain.

This register is required for CoreSight compliance.


PMPIDR1 is a 32-bit register.

Field descriptions

The PMPIDR1 bit assignments are:


Bits [31:8]

Reserved, RES0.

DES_0, bits [7:4]

Designer, least significant nibble of JEP106 ID code. For Arm Limited, this field is 0b1011.

PART_1, bits [3:0]

Part number, most significant nibble.

Accessing the PMPIDR1

PMPIDR1 can be accessed through the external debug interface:


This interface is accessible as follows:

  • When FEAT_DoPD is not implemented or IsCorePowered() accesses to this register are RO.
  • Otherwise accesses to this register generate an error response.