TRCIDR3, ID Register 3

The TRCIDR3 characteristics are:

Purpose

Returns the base architecture of the trace unit.

Configuration

External register TRCIDR3 bits [31:0] are architecturally mapped to AArch64 System register TRCIDR3[31:0] .

This register is present only when FEAT_ETE is implemented. Otherwise, direct accesses to TRCIDR3 are RES0.

Attributes

TRCIDR3 is a 32-bit register.

Field descriptions

The TRCIDR3 bit assignments are:

NOOVERFLOW, bit [31]

Indicates if overflow prevention is implemented.

NUMPROC, bits [13:12, 30:28]

Indicates the number of PEs available for tracing.

This field reads as 0b00000.

The NUMPROC field is split as follows:

• NUMPROC[2:0] is TRCIDR3[30:28].
• NUMPROC[4:3] is TRCIDR3[13:12].

SYSSTALL, bit [27]

Indicates if stalling of the PE is permitted.

The value of this field might be dynamic and change based on system conditions.

If TRCIDR3.STALLCTL == 0b0 then this field is 0b0.

STALLCTL, bit [26]

Indicates if trace unit implements stalling of the PE.

SYNCPR, bit [25]

Indicates if an implementation has a fixed synchronization period.

This bit reads as 0b0.

TRCERR, bit [24]

Indicates forced tracing of System Error exceptions is implemented.

This bit reads as 0b1.

Bit [23]

Reserved, RES0.

EXLEVEL_NS_EL2, bit [22]

Indicates if Non-secure EL2 implemented.

EXLEVEL_NS_EL1, bit [21]

Indicates if Non-secure EL1 implemented.

EXLEVEL_NS_EL0, bit [20]

Indicates if Non-secure EL0 implemented.

EXLEVEL_S_EL3, bit [19]

Indicates if Secure EL3 implemented.

EXLEVEL_S_EL2, bit [18]

Indicates if Secure EL2 implemented.

EXLEVEL_S_EL1, bit [17]

Indicates if Secure EL1 implemented.

EXLEVEL_S_EL0, bit [16]

Indicates if Secure EL0 implemented.

Bits [15:14]

Reserved, RES0.

CCITMIN, bits [11:0]

Indicates the minimum value that can be programmed in TRCCCCTLR.THRESHOLD.

If TRCIDR0.TRCCCI == 0b1 then the minimum value of this field is 0x001.

If TRCIDR0.TRCCCI == 0b0 then this field is zero.

Accessing the TRCIDR3

TRCIDR3 can be accessed through the external debug interface:

This interface is accessible as follows:

• When OSLockStatus() or !IsTraceCorePowered() accesses to this register generate an error response.
• Otherwise accesses to this register are RO.