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TRCPDCR, PowerDown Control Register
The TRCPDCR characteristics are:
Purpose
Requests the system to provide power to the trace unit.
Configuration
This register is present only when FEAT_ETE is implemented. Otherwise, direct accesses to TRCPDCR are RES0.
Attributes
TRCPDCR is a 32-bit register.
Field descriptions
The TRCPDCR bit assignments are:
Bits [31:4]
Reserved, RES0.
PU, bit [3]
Power Up Request.
| PU | Meaning |
|---|---|
| 0b0 |
The system can remove power from the trace unit core power domain, or requests for power to the trace unit core power domain are implemented outside of the trace unit. |
| 0b1 |
The system must provide power to the trace unit core power domain. |
This bit is RES0.
Bits [2:0]
Reserved, RES0.
Accessing the TRCPDCR
External debugger accesses to this register are unaffected by the OS Lock.
TRCPDCR can be accessed through the external debug interface:
| Component | Offset |
|---|---|
| ETE | 0x310 |
This interface is accessible as follows:
- When !IsTraceCorePowered() accesses to this register generate an error response.
- Otherwise accesses to this register are RW.