TLBIIPAS2, TLB Invalidate by Intermediate Physical Address, Stage 2
The TLBIIPAS2 characteristics are:
Purpose
If EL2 is implemented, invalidate all cached copies of translation table entries from TLBs that meet the following requirements:
- The entry is a stage 2 only translation table entry, from any level of the translation table walk.
- SCR.NS is 1.
- The entry would be used for the specified IPA.
- The entry would be used with the current VMID.
- The entry would be required for the PL1&0 translation regime.
The invalidation is not required to apply to caching structures that combine stage 1 and stage 2 translation table entries.
The invalidation only applies to the PE that executes this System instruction.
Configuration
This System instruction is not implemented in architecture versions before Armv8.
Attributes
TLBIIPAS2 is a 32-bit System instruction.
Field descriptions
The TLBIIPAS2 input value bit assignments are:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | IPA[39:12] | ||||||||||||||||||||||||||||||
Bits [31:28]
Reserved, RES0.
IPA[39:12], bits [27:0]
Bits[39:12] of the intermediate physical address to match.
Executing the TLBIIPAS2 instruction
If this instruction is executed in a Secure privileged mode other than Monitor mode, then the behavior is CONSTRAINED UNPREDICTABLE, and one of the following behaviors must occur:
- The instruction is UNDEFINED.
- The instruction is treated as a NOP.
- The instruction executes as if it had been executed in Monitor mode.
Accesses to this instruction use the following encodings:
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b100 | 0b1000 | 0b0100 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T8 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T8 == '1' then
AArch32.TakeHypTrapException(0x03);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
TLBIIPAS2(R[t]);
elsif PSTATE.EL == EL3 then
if !HaveEL(EL2) then
UNDEFINED;
elsif SCR.NS == '0' then
//no operation
else
TLBIIPAS2(R[t]);