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TRBBASER_EL1, Trace Buffer Base Address Register

The TRBBASER_EL1 characteristics are:

Purpose

Defines the base address for the trace buffer.

Configuration

This register is present only when TRBE is implemented. Otherwise, direct accesses to TRBBASER_EL1 are UNDEFINED.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

TRBBASER_EL1 is a 64-bit register.

Field descriptions

The TRBBASER_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
BASE
BASERES0
313029282726252423222120191817161514131211109876543210

BASE, bits [63:12]

Trace Buffer Base pointer address. (TRBBASER_EL1.BASE << 12) is the address of the first byte in the trace buffer. Bits [11:0] of the Base pointer address are always zero. If the smallest implemented translation granule is not 4KB, then TRBBASER_EL1[N-1:12] are RES0, where N is the IMPLEMENTATION DEFINED value Log2(smallest implemented translation granule).

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Bits [11:0]

Reserved, RES0.

Accessing the TRBBASER_EL1

The PE might ignore a direct write to TRBBASER_EL1 if TRBLIMITR_EL1.E == 1.

Accesses to this register use the following encodings:

MRS <Xt>, TRBBASER_EL1

op0op1CRnCRmop2
0b110b0000b10010b10110b010
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && !ELUsingAArch32(EL2) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.TRBBASER_EL1 == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.E2TB == 'x0' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSTB != '01' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSTB != '11' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return TRBBASER_EL1;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSTB != '01' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSTB != '11' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return TRBBASER_EL1;
elsif PSTATE.EL == EL3 then
    return TRBBASER_EL1;
              

MSR TRBBASER_EL1, <Xt>

op0op1CRnCRmop2
0b110b0000b10010b10110b010
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && !ELUsingAArch32(EL2) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.TRBBASER_EL1 == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.E2TB == 'x0' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSTB != '01' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSTB != '11' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        TRBBASER_EL1 = X[t];
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSTB != '01' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSTB != '11' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        TRBBASER_EL1 = X[t];
elsif PSTATE.EL == EL3 then
    TRBBASER_EL1 = X[t];
              


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