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TRBIDR_EL1, Trace Buffer ID Register

The TRBIDR_EL1 characteristics are:

Purpose

Describes constraints on using the Trace Buffer Extension to software, including whether the Trace Buffer Extension can be programmed at the current Exception level.

Configuration

This register is present only when TRBE is implemented. Otherwise, direct accesses to TRBIDR_EL1 are UNDEFINED.

Attributes

TRBIDR_EL1 is a 64-bit register.

Field descriptions

The TRBIDR_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
RES0FPAlign
313029282726252423222120191817161514131211109876543210

Bits [63:6]

Reserved, RES0.

F, bit [5]

Flag Updates. Defines whether the address translation performed by the Trace Buffer Extension manages the Access Flag and dirty state.

FMeaning
0b0

Trace buffer address translation does not manage the Access flag and dirty state in translation tables.

0b1

Trace buffer address translation manages the Access Flag and dirty state in the same way as the MMU on this PE.

P, bit [4]

Programming not allowed. The trace buffer is owned by a higher Exception level or by the other Security state.

PMeaning
0b0

The owning Exception level is the current Exception level or a lower Exception level, and the owning Security state is the current Security state.

0b1

The owning Exception level is a higher Exception level, or the owning Security state is not the current Security state.

The value read from this field depends on the current Exception level and the values of MDCR_EL3.NSTB and MDCR_EL2.E2TB:

  • If EL3 is implemented and either MDCR_EL3.NSTB == 0b00 or MDCR_EL3.NSTB == 0b01, meaning the owning Security state is Secure state, this bit reads as one from:

    • Non-secure EL2.

    • Non-secure EL1.

    • If Secure EL2 is implemented and enabled, and MDCR_EL2.E2TB == 0b00, Secure EL1.

  • If EL3 is implemented and either MDCR_EL3.NSTB == 0b10 or MDCR_EL3.NSTB == 0b11, meaning the owning Security state is Non-secure state, this bit reads as one from:

    • Secure EL1.

    • If Secure EL2 is implemented, Secure EL2.

    • If EL2 is implemented and MDCR_EL2.E2TB == 0b00, Non-secure EL1.

  • If EL3 is not implemented, EL2 is implemented, and MDCR_EL2.E2TB == 0b00, this bit reads as one from EL1.

Otherwise, this bit reads as zero.

Align, bits [3:0]

Defines the minimum alignment constraint for writes to TRBPTR_EL1 and TRBTRG_EL1.

AlignMeaning
0b0000

Byte.

0b0001

Halfword.

0b0010

Word.

0b0011

Doubleword.

0b0100

16 bytes.

0b0101

32 bytes.

0b0110

64 bytes.

0b0111

128 bytes.

0b1000

256 bytes.

0b1001

512 bytes.

0b1010

1KB.

0b1011

2KB.

All other values are reserved.

Accessing the TRBIDR_EL1

Accesses to this register use the following encodings:

MRS <Xt>, TRBIDR_EL1

op0op1CRnCRmop2
0b110b0000b10010b10110b111
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && !ELUsingAArch32(EL2) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.TRBIDR_EL1 == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        return TRBIDR_EL1;
elsif PSTATE.EL == EL2 then
    return TRBIDR_EL1;
elsif PSTATE.EL == EL3 then
    return TRBIDR_EL1;
              


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