You copied the Doc URL to your clipboard.

TRCIDR0, ID Register 0

The TRCIDR0 characteristics are:

Purpose

Returns the tracing capabilities of the trace unit.

Configuration

AArch64 System register TRCIDR0 bits [31:0] are architecturally mapped to External register TRCIDR0[31:0] .

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCIDR0 are UNDEFINED.

Attributes

TRCIDR0 is a 64-bit register.

Field descriptions

The TRCIDR0 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
RES0COMMTRANSCOMMOPTTSSIZERES0TRCEXDATAQSUPPQFILTCONDTYPENUMEVENTRETSTACKRES0TRCCCITRCCONDTRCBBTRCDATAINSTP0RES1
313029282726252423222120191817161514131211109876543210

Bits [63:31]

Reserved, RES0.

COMMTRANS, bit [30]

Transaction Start element behavior.

COMMTRANSMeaning
0b0

Transaction Start elements are P0 elements.

0b1

Transaction Start elements are not P0 elements.

COMMOPT, bit [29]

Indicates how the commit field in Cycle count packets is interpreted.

COMMOPTMeaning
0b0

Commit mode 0.

Cycle count packets includes the Commit element to which the Cycle Count element is attached.

0b1

Commit mode 1.

Cycle count packets do not include Commit elements. The Cycle Count element is attached to the most recent Commit element.

This bit reads-as-one if TRCIDR0.TRCCCI == 0b1 and TRCIDR8.MAXSPEC == 0x0. This bit reads-as-zero if TRCIDR0.TRCCCI == 0b0.

TSSIZE, bits [28:24]

Indicates that the trace unit implements Global timestamping and the size of the timestamp value.

TSSIZEMeaning
0b00000

Global timestamping not implemented.

0b01000

Global timestamping implemented with a 64-bit timestamp value.

All other values are reserved.

This field reads as 0b01000.

Bits [23:18]

Reserved, RES0.

TRCEXDATA, bit [17]

When TRCIDR0.TRCDATA != 0b00:

Indicates if the trace unit implements tracing of data transfers for exceptions and exception returns. Data tracing is not implemented in ETE and this field is reserved for other trace architectures. Allocated in other trace architectures.

TRCEXDATAMeaning
0b0

Tracing of data transfers for exceptions and exception returns not implemented.

0b1

Tracing of data transfers for exceptions and exception returns implemented.


Otherwise:

Reserved, RES0.

QSUPP, bits [16:15]

Indicates that the trace unit implements Q element support.

QSUPPMeaning
0b00

Q element support is not implemented.

0b01

Q element support is implemented, and only supports Q elements with instruction counts.

0b10

Q element support is implemented, and only supports Q elements without instruction counts.

0b11

Q element support is implemented, and supports:

  • Q elements with instruction counts.
  • Q elements without instruction counts.

QFILT, bit [14]

When TRCIDR0.QSUPP != 0b00:

Indicates if the trace unit implements Q element filtering.

QFILTMeaning
0b0

Q element filtering is not implemented.

0b1

Q element filtering is implemented.


Otherwise:

Reserved, RES0.

CONDTYPE, bits [13:12]

When TRCIDR0.TRCCOND == 0b1:

Indicates how conditional instructions are traced. Conditional instruction tracing is not implemented in ETE and this field is reserved for other trace architectures. Allocated in other trace architectures.

CONDTYPEMeaning
0b00

Conditional instructions are traced with an indication of whether they pass or fail their condition code check.

0b01

Conditional instructions are traced with an indication of the APSR condition flags.

All other values are reserved.


Otherwise:

Reserved, RES0.

NUMEVENT, bits [11:10]

When TRCIDR4.NUMRSPAIR == 0b0000:

Indicates the number of ETEEvents implemented.

NUMEVENTMeaning
0b00

The trace unit supports 0 ETEEvents.

All other values are reserved.


When TRCIDR4.NUMRSPAIR != 0b0000:

Indicates the number of ETEEvents implemented.

NUMEVENTMeaning
0b00

The trace unit supports 1 ETEEvent.

0b01

The trace unit supports 2 ETEEvents.

0b10

The trace unit supports 3 ETEEvents.

0b11

The trace unit supports 4 ETEEvents.


Otherwise:

Reserved, RES0.

RETSTACK, bit [9]

Indicates if the trace unit supports the return stack.

RETSTACKMeaning
0b0

Return stack not implemented.

0b1

Return stack implemented.

Bit [8]

Reserved, RES0.

TRCCCI, bit [7]

Indicates if the trace unit implements cycle counting.

TRCCCIMeaning
0b0

Cycle counting not implemented.

0b1

Cycle counting implemented.

This bit reads as 0b1.

TRCCOND, bit [6]

Indicates if the trace unit implements conditional instruction tracing. Conditional instruction tracing is not implemented in ETE and this field is reserved for other trace architectures.

TRCCONDMeaning
0b0

Conditional instruction tracing not implemented.

0b1

Conditional instruction tracing implemented.

This bit reads as 0b0.

TRCBB, bit [5]

Indicates if the trace unit implements branch broadcasting.

TRCBBMeaning
0b0

Branch broadcasting not implemented.

0b1

Branch broadcasting implemented.

This bit reads as 0b1.

TRCDATA, bits [4:3]

Indicates if the trace unit implements data tracing. Data tracing is not implemented in ETE and this field is reserved for other trace architectures.

TRCDATAMeaning
0b00

Data tracing not implemented.

0b11

Data tracing implemented.

All other values are reserved.

This field reads as 0b00.

INSTP0, bits [2:1]

Indicates if load and store instructions are P0 instructions. Load and store instructions as P0 instructions is not implemented in ETE and this field is reserved for other trace architectures.

INSTP0Meaning
0b00

Load and store instructions are not P0 instructions.

0b11

Load and store instructions are P0 instructions.

All other values are reserved.

This field reads as 0b00.

Bit [0]

Reserved, RES1.

Accessing the TRCIDR0

Accesses to this register use the following encodings:

MRS <Xt>, TRCIDR0

op0op1CRnCRmop2
0b100b0010b00000b10000b111
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if CPACR_EL1.TTA == '1' then
        AArch64.SystemAccessTrap(EL1, 0x18);
    elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TTA == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() && !ELUsingAArch32(EL2) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.TRCID == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return TRCIDR0;
elsif PSTATE.EL == EL2 then
    if CPTR_EL2.TTA == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return TRCIDR0;
elsif PSTATE.EL == EL3 then
    if CPTR_EL3.TTA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return TRCIDR0;
              


Was this page helpful? Yes No