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TRCIMSPEC0, IMP DEF Register 0

The TRCIMSPEC0 characteristics are:

Purpose

TRCIMSPEC0 shows the presence of any IMPLEMENTATION DEFINED features, and provides an interface to enable the features that are provided.

Configuration

AArch64 System register TRCIMSPEC0 bits [31:0] are architecturally mapped to External register TRCIMSPEC0[31:0] .

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCIMSPEC0 are UNDEFINED.

Attributes

TRCIMSPEC0 is a 64-bit register.

Field descriptions

The TRCIMSPEC0 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
RES0ENSUPPORT
313029282726252423222120191817161514131211109876543210

Bits [63:8]

Reserved, RES0.

EN, bits [7:4]

When TRCIMSPEC0.SUPPORT != 0b0000:

Enable. Controls whether the IMPLEMENTATION DEFINED features are enabled.

ENMeaning
0b0000

The IMPLEMENTATION DEFINED features are not enabled. The trace unit must behave as if the IMPLEMENTATION DEFINED features are not supported.

0b0001

The trace unit behavior is IMPLEMENTATION DEFINED.

0b0010

The trace unit behavior is IMPLEMENTATION DEFINED.

0b0011

The trace unit behavior is IMPLEMENTATION DEFINED.

0b0100

The trace unit behavior is IMPLEMENTATION DEFINED.

0b0101

The trace unit behavior is IMPLEMENTATION DEFINED.

0b0110

The trace unit behavior is IMPLEMENTATION DEFINED.

0b0111

The trace unit behavior is IMPLEMENTATION DEFINED.

0b1000

The trace unit behavior is IMPLEMENTATION DEFINED.

0b1001

The trace unit behavior is IMPLEMENTATION DEFINED.

0b1010

The trace unit behavior is IMPLEMENTATION DEFINED.

0b1011

The trace unit behavior is IMPLEMENTATION DEFINED.

0b1100

The trace unit behavior is IMPLEMENTATION DEFINED.

0b1101

The trace unit behavior is IMPLEMENTATION DEFINED.

0b1110

The trace unit behavior is IMPLEMENTATION DEFINED.

0b1111

The trace unit behavior is IMPLEMENTATION DEFINED.

On a Trace unit reset, this field resets to 0.


Otherwise:

Reserved, RES0.

SUPPORT, bits [3:0]

Indicates whether the implementation supports IMPLEMENTATION DEFINED features.

SUPPORTMeaning
0b0000

No IMPLEMENTATION DEFINED features are supported.

0b0001

IMPLEMENTATION DEFINED features are supported.

0b0010

IMPLEMENTATION DEFINED features are supported.

0b0011

IMPLEMENTATION DEFINED features are supported.

0b0100

IMPLEMENTATION DEFINED features are supported.

0b0101

IMPLEMENTATION DEFINED features are supported.

0b0110

IMPLEMENTATION DEFINED features are supported.

0b0111

IMPLEMENTATION DEFINED features are supported.

0b1000

IMPLEMENTATION DEFINED features are supported.

0b1001

IMPLEMENTATION DEFINED features are supported.

0b1010

IMPLEMENTATION DEFINED features are supported.

0b1011

IMPLEMENTATION DEFINED features are supported.

0b1100

IMPLEMENTATION DEFINED features are supported.

0b1101

IMPLEMENTATION DEFINED features are supported.

0b1110

IMPLEMENTATION DEFINED features are supported.

0b1111

IMPLEMENTATION DEFINED features are supported.

Use of nonzero values requires written permission from Arm.

Access to this field is RO.

Accessing the TRCIMSPEC0

Accesses to this register use the following encodings:

MRS <Xt>, TRCIMSPEC0

op0op1CRnCRmop2
0b100b0010b00000b00000b111
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if CPACR_EL1.TTA == '1' then
        AArch64.SystemAccessTrap(EL1, 0x18);
    elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TTA == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() && !ELUsingAArch32(EL2) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.TRCIMSPECn == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return TRCIMSPEC0;
elsif PSTATE.EL == EL2 then
    if CPTR_EL2.TTA == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return TRCIMSPEC0;
elsif PSTATE.EL == EL3 then
    if CPTR_EL3.TTA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return TRCIMSPEC0;
              

MSR TRCIMSPEC0, <Xt>

op0op1CRnCRmop2
0b100b0010b00000b00000b111
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if CPACR_EL1.TTA == '1' then
        AArch64.SystemAccessTrap(EL1, 0x18);
    elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TTA == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() && !ELUsingAArch32(EL2) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.TRCIMSPECn == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        TRCIMSPEC0 = X[t];
elsif PSTATE.EL == EL2 then
    if CPTR_EL2.TTA == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        TRCIMSPEC0 = X[t];
elsif PSTATE.EL == EL3 then
    if CPTR_EL3.TTA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        TRCIMSPEC0 = X[t];
              


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