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TRCSYNCPR, Synchronization Period Register

The TRCSYNCPR characteristics are:

Purpose

Controls how often trace protocol synchronization requests occur.

Configuration

AArch64 System register TRCSYNCPR bits [31:0] are architecturally mapped to External register TRCSYNCPR[31:0] .

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCSYNCPR are UNDEFINED.

Attributes

TRCSYNCPR is a 64-bit register.

Field descriptions

The TRCSYNCPR bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
RES0PERIOD
313029282726252423222120191817161514131211109876543210

Bits [63:5]

Reserved, RES0.

PERIOD, bits [4:0]

Defines the number of bytes of trace between each periodic trace protocol synchronization request.

PERIODMeaning
0b00000

Trace protocol synchronization is disabled.

0b01000

Trace protocol synchronization request occurs after 28 bytes of trace.

0b01001

Trace protocol synchronization request occurs after 29 bytes of trace.

0b01010

Trace protocol synchronization request occurs after 210 bytes of trace.

0b01011

Trace protocol synchronization request occurs after 211 bytes of trace.

0b01100

Trace protocol synchronization request occurs after 212 bytes of trace.

0b01101

Trace protocol synchronization request occurs after 213 bytes of trace.

0b01110

Trace protocol synchronization request occurs after 214 bytes of trace.

0b01111

Trace protocol synchronization request occurs after 215 bytes of trace.

0b10000

Trace protocol synchronization request occurs after 216 bytes of trace.

0b10001

Trace protocol synchronization request occurs after 217 bytes of trace.

0b10010

Trace protocol synchronization request occurs after 218 bytes of trace.

0b10011

Trace protocol synchronization request occurs after 219 bytes of trace.

0b10100

Trace protocol synchronization request occurs after 220 bytes of trace.

Other values are reserved. If a reserved value is programmed into PERIOD, then the behavior of the synchronization period counter is CONSTRAINED UNPREDICTABLE and one of the following behaviors occurs:

  • No trace protocol synchronization requests are generated by this counter.
  • Trace protocol synchronization requests occur at the specified period.
  • Trace protocol synchronization requests occur at some other UNKNOWN period which can vary.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

Accessing the TRCSYNCPR

Must be programmed if TRCIDR3.SYNCPR == 0b0.

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

Accesses to this register use the following encodings:

MRS <Xt>, TRCSYNCPR

op0op1CRnCRmop2
0b100b0010b00000b11010b000
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if CPACR_EL1.TTA == '1' then
        AArch64.SystemAccessTrap(EL1, 0x18);
    elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TTA == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() && !ELUsingAArch32(EL2) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.TRC == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return TRCSYNCPR;
elsif PSTATE.EL == EL2 then
    if CPTR_EL2.TTA == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return TRCSYNCPR;
elsif PSTATE.EL == EL3 then
    if CPTR_EL3.TTA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return TRCSYNCPR;
              

MSR TRCSYNCPR, <Xt>

op0op1CRnCRmop2
0b100b0010b00000b11010b000
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if CPACR_EL1.TTA == '1' then
        AArch64.SystemAccessTrap(EL1, 0x18);
    elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TTA == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() && !ELUsingAArch32(EL2) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.TRC == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        TRCSYNCPR = X[t];
elsif PSTATE.EL == EL2 then
    if CPTR_EL2.TTA == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        TRCSYNCPR = X[t];
elsif PSTATE.EL == EL3 then
    if CPTR_EL3.TTA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        TRCSYNCPR = X[t];
              


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