PMDEVARCH, Performance Monitors Device Architecture register
The PMDEVARCH characteristics are:
Identifies the programmers' model architecture of the Performance Monitor component.
It is IMPLEMENTATION DEFINED whether PMDEVARCH is implemented in the Core power domain or in the Debug power domain.
If ARMv8.3-DoPD is implemented, this register is in the Core power domain. If ARMv8.3-DoPD is not implemented, this register is in the Debug power domain.
PMDEVARCH is a 32-bit register.
The PMDEVARCH bit assignments are:
ARCHITECT, bits [31:21]
Defines the architecture of the component. For Performance Monitors, this is Arm Limited.
Bits [31:28] are the JEP106 continuation code, 0x4.
Bits [27:21] are the JEP106 ID code, 0x3B.
PRESENT, bit 
When set to 1, indicates that the DEVARCH is present.
This field is 1 in Armv8.
REVISION, bits [19:16]
Defines the architecture revision. For architectures defined by Arm this is the minor revision.
For Performance Monitors, the revision defined by Armv8 is 0x0.
All other values are reserved.
ARCHID, bits [15:0]
Defines this part to be an Armv8 debug component. For architectures defined by Arm this is further subdivided.
For Performance Monitors:
- Bits [15:12] are the architecture version, 0x2.
- Bits [11:0] are the architecture part number, 0xA16.
This corresponds to Performance Monitors architecture version PMUv3.
The PMUv3 memory-mapped programmers' model can be used by devices other than Armv8 processors. Software must determine whether the PMU is attached to an Armv8 processor by using the PMDEVAFF0 and PMDEVAFF1 registers to discover the affinity of the PMU to any Armv8 processors.
Accessing the PMDEVARCH
PMDEVARCH can be accessed through the external debug interface:
This interface is accessible as follows:
- When ARMv8.3-DoPD is not implemented or IsCorePowered() accesses to this register are RO.
- Otherwise accesses to this register generate an error response.