You copied the Doc URL to your clipboard.

TRCACVR<n>, Address Comparator Value Register <n>, n = 0 - 15

The TRCACVR<n> characteristics are:


Contains the address value.


External register TRCACVR<n> bits [63:0] are architecturally mapped to AArch64 System register TRCACVR<n>[63:0] .

RW fields in this register reset to architecturally UNKNOWN values.

This register is present only when ETE is implemented and TRCIDR4.NUMACPAIRS * 2 > n. Otherwise, direct accesses to TRCACVR<n> are RES0.


TRCACVR<n> is a 64-bit register.

Field descriptions

The TRCACVR<n> bit assignments are:


ADDRESS, bits [63:0]

Address Value.

The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field, then the address must be zero-extended to the ADDRESS field width. The trace unit then compares all implemented bits. For example, in a system that supports both 32-bit and 64-bit addresses, when the PE is in AArch32 state the comparator must zero-extend the 32-bit address and compare against the full 64 bits that are stored in the TRCACVR<n>. This requires that the trace analyzer always programs all implemented bits of the TRCACVR<n>.

The result of writing a value other than all zeros or all ones to ADDRESS at bits[63:P] is an UNKNOWN value, where P is defined as the virtual address size supported by the PE.

The result of writing a value of all zeros or all ones to ADDRESS at bits[63:P] is the written value, and a read of the register returns the written value.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

Accessing the TRCACVR<n>

Must be programmed if any of the following are true:

  • TRCBBCTLR.RANGE[n/2] == 0b1.

  • TRCRSCTLR<a>.GROUP == 0b0100 and TRCRSCTLR<a>.SAC[n] == 0b1.

  • TRCRSCTLR<a>.GROUP == 0b0101 and TRCRSCTLR<a>.ARC[n/2] == 0b1.

  • TRCVIIECTLR.EXCLUDE[n/2] == 0b1.

  • TRCVIIECTLR.INCLUDE[n/2] == 0b1.

  • TRCVISSCTLR.START[n] == 0b1.

  • TRCVISSCTLR.STOP[n] == 0b1.

  • TRCSSCCR<>.ARC[n/2] == 0b1.

  • TRCSSCCR<>.SAC[n] == 0b1.

  • TRCQCTLR.RANGE[n/2] == 0b1.

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

TRCACVR<n> can be accessed through the external debug interface:

ETE0x400 + 8n

This interface is accessible as follows:

  • When !AllowExternalTraceAccess(), or OSLockStatus() or !IsTraceCorePowered() accesses to this register generate an error response.
  • Otherwise accesses to this register are RW.

Was this page helpful? Yes No