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TRCCIDCVR<n>, Context Identifier Comparator Value Registers <n>, n = 0 - 7

The TRCCIDCVR<n> characteristics are:

Purpose

Contains a Context identifier value.

Configuration

External register TRCCIDCVR<n> bits [63:0] are architecturally mapped to AArch64 System register TRCCIDCVR<n>[63:0] .

RW fields in this register reset to architecturally UNKNOWN values.

This register is present only when ETE is implemented and TRCIDR4.NUMCIDC > n. Otherwise, direct accesses to TRCCIDCVR<n> are RES0.

Attributes

TRCCIDCVR<n> is a 64-bit register.

Field descriptions

The TRCCIDCVR<n> bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
VALUE
VALUE
313029282726252423222120191817161514131211109876543210

VALUE, bits [63:0]

Context identifier value. The width of this field is indicated by TRCIDR2.CIDSIZE. Unimplemented bits are RES0. After a PE Reset, the trace unit assumes that the Context identifier is zero until the PE updates the Context identifier.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

Accessing the TRCCIDCVR<n>

Must be programmed if any of the following are true:

  • TRCRSCTLR<a>.GROUP == 0b0110 and TRCRSCTLR<a>.CID[n] == 0b1.

  • TRCACATR<a>.CONTEXTTYPE == 0b01 or 0b11 and TRCACATR<a>.CONTEXT == n.

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

TRCCIDCVR<n> can be accessed through the external debug interface:

ComponentOffset
ETE0x600 + 8n

This interface is accessible as follows:

  • When !AllowExternalTraceAccess(), or OSLockStatus() or !IsTraceCorePowered() accesses to this register generate an error response.
  • Otherwise accesses to this register are RW.


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