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TRCCIDR0, Component Identification Register 0

The TRCCIDR0 characteristics are:

Purpose

Provides discovery information for the component.

For additional information see the CoreSight Architecture Specification.

Configuration

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCCIDR0 are RES0.

There are no configuration notes.

Attributes

TRCCIDR0 is a 32-bit register.

Field descriptions

The TRCCIDR0 bit assignments are:

313029282726252423222120191817161514131211109876543210
RES0PRMBL_0

Bits [31:8]

Reserved, RES0.

PRMBL_0, bits [7:0]

Component identification preamble, segment 0.

This field reads as 0x0D.

Accessing the TRCCIDR0

External debugger accesses to this register are unaffected by the OS Lock.

TRCCIDR0 can be accessed through the external debug interface:

ComponentOffset
ETE0xFF0

This interface is accessible as follows:

  • When !IsTraceCorePowered() accesses to this register generate an error response.
  • Otherwise accesses to this register are RO.


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