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TRCCONFIGR, Trace Configuration Register

The TRCCONFIGR characteristics are:

Purpose

Controls the tracing options.

Configuration

External register TRCCONFIGR bits [31:0] are architecturally mapped to AArch64 System register TRCCONFIGR[31:0] .

RW fields in this register reset to architecturally UNKNOWN values.

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCCONFIGR are RES0.

Attributes

TRCCONFIGR is a 32-bit register.

Field descriptions

The TRCCONFIGR bit assignments are:

313029282726252423222120191817161514131211109876543210
RES0RES0QERSTSRES0VMIDCIDRES0CCIBBRES0RES1

Bits [31:16]

Reserved, RES0.

Bit [15]

When TRCIDR2.VMIDOPT == 0b00:

Reserved, RES0.

Virtual context identifier selection control.

VTTBR_EL2.VMID is used as the Virtual context identifier.


When TRCIDR2.VMIDOPT == 0b10:

Reserved, RES1.

Virtual context identifier selection control.

CONTEXTIDR_EL2.PROCID is used as the Virtual context identifier.


When TRCIDR2.VMIDOPT == 0b01:

Virtual context identifier selection control.

VMIDOPTMeaning
0b0

VTTBR_EL2.VMID is used as the Virtual context identifier.

0b1

CONTEXTIDR_EL2.PROCID is used as the Virtual context identifier.


Otherwise:

Reserved, RES0.

QE, bits [14:13]

When TRCIDR0.QSUPP == 0b01:

Q element generation control.

QEMeaning
0b00

Q elements are disabled.

0b01

Q elements with instruction counts are enabled.

Q elements without instruction counts are disabled.

All other values are reserved.


When TRCIDR0.QSUPP == 0b10:

Q element generation control.

QEMeaning
0b00

Q elements are disabled.

0b11

Q elements with instruction counts are enabled.

Q elements without instruction counts are enabled.

All other values are reserved.


When TRCIDR0.QSUPP == 0b11:

Q element generation control.

QEMeaning
0b00

Q elements are disabled.

0b01

Q elements with instruction counts are enabled.

Q elements without instruction counts are disabled.

0b11

Q elements with instruction counts are enabled.

Q elements without instruction counts are enabled.

All other values are reserved.


Otherwise:

Reserved, RES0.

RS, bit [12]

When TRCIDR0.RETSTACK == 0b1:

Return stack control.

RSMeaning
0b0

Return stack is disabled.

0b1

Return stack is enabled.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

TS, bit [11]

When TRCIDR0.TSSIZE != 0b00000:

Global timestamp tracing control.

TSMeaning
0b0

Global timestamp tracing is disabled.

0b1

Global timestamp tracing is enabled.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

Bits [10:8]

Reserved, RES0.

VMID, bit [7]

When TRCIDR2.VMIDSIZE != 0b00000:

Virtual context identifier tracing control.

VMIDMeaning
0b0

Virtual context identifier tracing is disabled.

0b1

Virtual context identifier tracing is enabled.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

CID, bit [6]

When TRCIDR2.CIDSIZE != 0b00000:

Context identifier tracing control.

CIDMeaning
0b0

Context identifier tracing is disabled.

0b1

Context identifier tracing is enabled.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

Bit [5]

Reserved, RES0.

CCI, bit [4]

When TRCIDR0.TRCCCI == 0b1:

Cycle counting instruction tracing control.

CCIMeaning
0b0

Cycle counting instruction tracing is disabled.

0b1

Cycle counting instruction tracing is enabled.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

BB, bit [3]

When TRCIDR0.TRCBB == 0b1:

Branch broadcasting control.

BBMeaning
0b0

Branch broadcasting is disabled.

0b1

Branch broadcasting is enabled.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

Bits [2:1]

Reserved, RES0.

Bit [0]

Reserved, RES1.

Accessing the TRCCONFIGR

Must always be programmed.

TRCCONFIGR.QE must be set to 0b00 if TRCCONFIGR.BB is not 0b0.

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

TRCCONFIGR can be accessed through the external debug interface:

ComponentOffset
ETE0x010

This interface is accessible as follows:

  • When !AllowExternalTraceAccess(), or OSLockStatus() or !IsTraceCorePowered() accesses to this register generate an error response.
  • Otherwise accesses to this register are RW.


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