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TRCDEVAFF, Device Affinity Register

The TRCDEVAFF characteristics are:

Purpose

For additional information see the CoreSight Architecture Specification.

Reads the same value as the MPIDR_EL1 register for the PE this trace unit has affinity with.

Configuration

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCDEVAFF are RES0.

There are no configuration notes.

Attributes

TRCDEVAFF is a 64-bit register.

Field descriptions

The TRCDEVAFF bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
MPIDR_EL1
MPIDR_EL1
313029282726252423222120191817161514131211109876543210

MPIDR_EL1, bits [63:0]

Read-only copy of MPIDR_EL1, as seen from the highest implemented Exception level.

Accessing the TRCDEVAFF

External debugger accesses to this register are unaffected by the OS Lock.

TRCDEVAFF can be accessed through the external debug interface:

ComponentOffset
ETE0xFA8

This interface is accessible as follows:

  • When !IsTraceCorePowered() accesses to this register generate an error response.
  • Otherwise accesses to this register are RO.


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