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TRCLAR, Lock Access Register

The TRCLAR characteristics are:

Purpose

Used to lock and unlock the Software Lock.

Note that ETE does not implement the Software Lock.

For additional information see the CoreSight Architecture Specification.

Configuration

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCLAR are RES0.

There are no configuration notes.

Attributes

TRCLAR is a 32-bit register.

Field descriptions

The TRCLAR bit assignments are:

313029282726252423222120191817161514131211109876543210
KEY

KEY, bits [31:0]

When SoftwareLockStatus():

Software Lock Key.

A value of 0xC5ACCE55 unlocks the Software Lock.

Any other value locks the Software Lock.


Otherwise:

Reserved, RES0.

Accessing the TRCLAR

External debugger accesses to this register are unaffected by the OS Lock.

TRCLAR can be accessed through the external debug interface:

ComponentOffset
ETE0xFB0

This interface is accessible as follows:

  • When !IsTraceCorePowered() accesses to this register generate an error response.
  • Otherwise accesses to this register are WO.


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