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TRCPIDR7, Peripheral Identification Register 7

The TRCPIDR7 characteristics are:

Purpose

Provides discovery information for the component.

For additional information see the CoreSight Architecture Specification.

Configuration

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCPIDR7 are RES0.

There are no configuration notes.

Attributes

TRCPIDR7 is a 32-bit register.

Field descriptions

The TRCPIDR7 bit assignments are:

313029282726252423222120191817161514131211109876543210
RES0

Bits [31:0]

Reserved, RES0.

Accessing the TRCPIDR7

External debugger accesses to this register are unaffected by the OS Lock.

TRCPIDR7 can be accessed through the external debug interface:

ComponentOffset
ETE0xFDC

This interface is accessible as follows:

  • When !IsTraceCorePowered() accesses to this register generate an error response.
  • Otherwise accesses to this register are RO.


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