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TRCSSCSR<n>, Single-shot Comparator Control Status Register <n>, n = 0 - 7

The TRCSSCSR<n> characteristics are:

Purpose

Returns the status of the corresponding Single-shot Comparator Control.

Configuration

External register TRCSSCSR<n> bits [31:0] are architecturally mapped to AArch64 System register TRCSSCSR<n>[31:0] .

RW fields in this register reset to architecturally UNKNOWN values.

This register is present only when ETE is implemented and TRCIDR4.NUMSSCC > n. Otherwise, direct accesses to TRCSSCSR<n> are RES0.

Attributes

TRCSSCSR<n> is a 32-bit register.

Field descriptions

The TRCSSCSR<n> bit assignments are:

313029282726252423222120191817161514131211109876543210
STATUSPENDINGRES0PCDVDAINST

STATUS, bit [31]

Single-shot Comparator Control status. Indicates if any of the comparators selected by this Single-shot Comparator control have matched. The selected comparators are defined by TRCSSCCR<n>.ARC, TRCSSCCR<n>.SAC, and TRCSSPCICR<n>.PC.

STATUSMeaning
0b0

No match has occurred. When the first match occurs, this field takes a value of 0b1. It remains at 0b1 until explicitly modified by a write to this register.

0b1

One or more matches has occurred. If TRCSSCCR<n>.RST == 0b0 then:

  • There is only one match and no more matches are possible.
  • Software must reset this bit to 0b0 to re-enable the Single-shot Comparator Control.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

PENDING, bit [30]

Single-shot pending status. The Single-shot Comparator Control fired while the resources were in the Paused state.

PENDINGMeaning
0b0

No match has occurred.

0b1

One or more matches has occurred.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

Bits [29:4]

Reserved, RES0.

PC, bit [3]

PE Comparator Input support. Indicates if the Single-shot Comparator Control supports PE Comparator Inputs.

PCMeaning
0b0

This Single-shot Comparator Control does not support PE Comparator Inputs. Selecting any PE Comparator Inputs using the associated TRCSSPCICR<n> results in CONSTRAINED UNPREDICTABLE behavior of the Single-shot Comparator Control resource. The Single-shot Comparator Control might match unexpectedly or might not match.

0b1

This Single-shot Comparator Control supports PE Comparator Inputs.

Access to this field is RO.

DV, bit [2]

Data value comparator support. Data value comparisons are not implemented in ETE and are reserved for other trace architectures. Allocated in other trace architectures.

DVMeaning
0b0

This Single-shot Comparator Control does not support data value comparisons.

0b1

This Single-shot Comparator Control supports data value comparisons.

This bit reads as 0b0.

Access to this field is RO.

DA, bit [1]

Data address comparator support. Data address comparisons are not implemented in ETE and are reserved for other trace architectures. Allocated in other trace architectures.

DAMeaning
0b0

This Single-shot Comparator Control does not support data address comparisons.

0b1

This Single-shot Comparator Control supports data address comparisons.

This bit reads as 0b0.

Access to this field is RO.

INST, bit [0]

Instruction address comparator support. Indicates if the Single-shot Comparator Control supports instruction address comparisons.

INSTMeaning
0b0

This Single-shot Comparator Control does not support instruction address comparisons.

0b1

This Single-shot Comparator Control supports instruction address comparisons.

This bit reads as 0b1.

Access to this field is RO.

Accessing the TRCSSCSR<n>

Must be programmed if TRCRSCTLR<a>.GROUP == 0b0011 and TRCRSCTLR<a>.SINGLE_SHOT[n] == 0b1.

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

Reads from this register might return an UNKNOWN value if the trace unit is not in either of the Idle or Stable states.

TRCSSCSR<n> can be accessed through the external debug interface:

ComponentOffset
ETE0x2A0 + 4n

This interface is accessible as follows:

  • When !AllowExternalTraceAccess(), or OSLockStatus() or !IsTraceCorePowered() accesses to this register generate an error response.
  • Otherwise accesses to this register are RW.


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