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TRCVISSCTLR, ViewInst Start/Stop Control Register

The TRCVISSCTLR characteristics are:

Purpose

Use this to select, or read, the Single Address Comparators for the ViewInst start/stop function.

Configuration

External register TRCVISSCTLR bits [31:0] are architecturally mapped to AArch64 System register TRCVISSCTLR[31:0] .

RW fields in this register reset to architecturally UNKNOWN values.

This register is present only when ETE is implemented and TRCIDR4.NUMACPAIRS > 0b0000. Otherwise, direct accesses to TRCVISSCTLR are RES0.

Attributes

TRCVISSCTLR is a 32-bit register.

Field descriptions

The TRCVISSCTLR bit assignments are:

313029282726252423222120191817161514131211109876543210
STOP<m>, bit [m+16] START<m>, bit [m]

STOP<m>, bit [m+16], for m = 0 to 15

Selects which Single Address Comparators are in use with ViewInst start/stop function, for the purpose of stopping trace.

STOP<m>Meaning
0b0

The Single Address Comparator m, is not selected as a stop resource.

0b1

The Single Address Comparator m, is selected as a stop resource.

This bit is RES0 if m >= 2 × TRCIDR4.NUMACPAIRS.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

START<m>, bit [m], for m = 0 to 15

Selects which Single Address Comparators are in use with ViewInst start/stop function, for the purpose of starting trace.

START<m>Meaning
0b0

The Single Address Comparator m, is not selected as a start resource.

0b1

The Single Address Comparator m, is selected as a start resource.

This bit is RES0 if m >= 2 × TRCIDR4.NUMACPAIRS.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

Accessing the TRCVISSCTLR

Must be programmed if TRCIDR4.NUMACPAIRS > 0b0000.

For any 2 comparators selected for the ViewInst start/stop function, the comparator containing the lower address must be a lower numbered comparator.

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

TRCVISSCTLR can be accessed through the external debug interface:

ComponentOffset
ETE0x088

This interface is accessible as follows:

  • When !AllowExternalTraceAccess(), or OSLockStatus() or !IsTraceCorePowered() accesses to this register generate an error response.
  • Otherwise accesses to this register are RW.


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