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TRCVMIDCCTLR0, Virtual Context Identifier Comparator Control Register 0

The TRCVMIDCCTLR0 characteristics are:

Purpose

Virtual Context Identifier Comparator mask values for the TRCVMIDCVR<n> registers, where n=0-3.

Configuration

External register TRCVMIDCCTLR0 bits [31:0] are architecturally mapped to AArch64 System register TRCVMIDCCTLR0[31:0] .

RW fields in this register reset to architecturally UNKNOWN values.

This register is present only when ETE is implemented, TRCIDR4.NUMVMIDC > 0x0 and TRCIDR2.VMIDSIZE > 0b00000. Otherwise, direct accesses to TRCVMIDCCTLR0 are RES0.

Attributes

TRCVMIDCCTLR0 is a 32-bit register.

Field descriptions

The TRCVMIDCCTLR0 bit assignments are:

313029282726252423222120191817161514131211109876543210
COMP3<m>, bit [m+24] COMP2<m>, bit [m+16] COMP1<m>, bit [m+8] COMP0<m>, bit [m]

COMP3<m>, bit [m+24], for m = 0 to 7

When TRCIDR4.NUMVMIDC > 3:

TRCVMIDCVR3 mask control. Specifies the mask value that the trace unit applies to TRCVMIDCVR3. Each bit in this field corresponds to a byte in TRCVMIDCVR3.

COMP3<m>Meaning
0b0

The trace unit includes TRCVMIDCVR3[(m×8+7):(m×8)] when it performs the Virtual context identifier comparison.

0b1

The trace unit ignores TRCVMIDCVR3[(m×8+7):(m×8)] when it performs the Virtual context identifier comparison.

This bit is RES0 if m >= TRCIDR2.VMIDSIZE.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

COMP2<m>, bit [m+16], for m = 0 to 7

When TRCIDR4.NUMVMIDC > 2:

TRCVMIDCVR2 mask control. Specifies the mask value that the trace unit applies to TRCVMIDCVR2. Each bit in this field corresponds to a byte in TRCVMIDCVR2.

COMP2<m>Meaning
0b0

The trace unit includes TRCVMIDCVR2[(m×8+7):(m×8)] when it performs the Virtual context identifier comparison.

0b1

The trace unit ignores TRCVMIDCVR2[(m×8+7):(m×8)] when it performs the Virtual context identifier comparison.

This bit is RES0 if m >= TRCIDR2.VMIDSIZE.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

COMP1<m>, bit [m+8], for m = 0 to 7

When TRCIDR4.NUMVMIDC > 1:

TRCVMIDCVR1 mask control. Specifies the mask value that the trace unit applies to TRCVMIDCVR1. Each bit in this field corresponds to a byte in TRCVMIDCVR1.

COMP1<m>Meaning
0b0

The trace unit includes TRCVMIDCVR1[(m×8+7):(m×8)] when it performs the Virtual context identifier comparison.

0b1

The trace unit ignores TRCVMIDCVR1[(m×8+7):(m×8)] when it performs the Virtual context identifier comparison.

This bit is RES0 if m >= TRCIDR2.VMIDSIZE.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

COMP0<m>, bit [m], for m = 0 to 7

When TRCIDR4.NUMVMIDC > 0:

TRCVMIDCVR0 mask control. Specifies the mask value that the trace unit applies to TRCVMIDCVR0. Each bit in this field corresponds to a byte in TRCVMIDCVR0.

COMP0<m>Meaning
0b0

The trace unit includes TRCVMIDCVR0[(m×8+7):(m×8)] when it performs the Virtual context identifier comparison.

0b1

The trace unit ignores TRCVMIDCVR0[(m×8+7):(m×8)] when it performs the Virtual context identifier comparison.

This bit is RES0 if m >= TRCIDR2.VMIDSIZE.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

Accessing the TRCVMIDCCTLR0

If software uses the TRCVMIDCVR<n> registers, where n=0-3, then it must program this register.

If software sets a mask bit to 0b1 then it must program the relevant byte in TRCVMIDCVR<n> to 0x00.

If any bit is 0b1 and the relevant byte in TRCVMIDCVR<n> is not 0x00, the behavior of the Virtual Context Identifier Comparator is CONSTRAINED UNPREDICTABLE. In this scenario the comparator might match unexpectedly or might not match.

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

TRCVMIDCCTLR0 can be accessed through the external debug interface:

ComponentOffset
ETE0x688

This interface is accessible as follows:

  • When !AllowExternalTraceAccess(), or OSLockStatus() or !IsTraceCorePowered() accesses to this register generate an error response.
  • Otherwise accesses to this register are RW.


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