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Add the odd-numbered elements of the first source vector and the 1-bit carry from the least-significant bit of the odd-numbered elements of the second source vector to the even-numbered elements of the destination and accumulator vector. The 1-bit carry output is placed in the corresponding odd-numbered element of the destination vector.

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 0 1 0 1 0 sz 0 Zm 1 1 0 1 0 1 Zn Zda

#### SVE2

```if !HaveSVE2() then UNDEFINED;
integer esize = 32 << UInt(sz);
integer n = UInt(Zn);
integer m = UInt(Zm);
integer da = UInt(Zda);```

### Assembler Symbols

 Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.
<T> Is the size specifier, encoded in sz:
sz <T>
0 S
1 D
 Is the name of the first source scalable vector register, encoded in the "Zn" field.
 Is the name of the second source scalable vector register, encoded in the "Zm" field.

### Operation

```CheckSVEEnabled();
integer pairs = VL DIV (esize * 2);
bits(VL) operand = Z[n];
bits(VL) carries = Z[m];
bits(VL) result = Z[da];

for p = 0 to pairs-1
bits(esize) element1 = Elem[result, 2*p + 0, esize];
bits(esize) element2 = Elem[operand, 2*p + 1, esize];
bit carry_in = Elem[carries, 2*p + 1, esize]<0>;

(res, nzcv) = AddWithCarry(element1, element2, carry_in);
carry_out = nzcv<1>;

Elem[result, 2*p + 0, esize] = res;
Elem[result, 2*p + 1, esize] = ZeroExtend(carry_out);

Z[da] = result;```