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NBSL

Bitwise inverted select.

Selects bits from the first source vector where the corresponding bit in the third source vector is '1', and from the second source vector where the corresponding bit in the third source vector is '0'. The inverted result is placed destructively in the destination and first source vector. This instruction is unpredicated.

313029282726252423222120191817161514131211109876543210
00000100111Zm001111ZkZdn

SVE2

NBSL <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D

if !HaveSVE2() then UNDEFINED;
integer m = UInt(Zm);
integer k = UInt(Zk);
integer dn = UInt(Zdn);

Assembler Symbols

<Zdn>

Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.

<Zm>

Is the name of the second source scalable vector register, encoded in the "Zm" field.

<Zk>

Is the name of the third source scalable vector register, encoded in the "Zk" field.

Operation

CheckSVEEnabled();
bits(VL) operand1 = Z[dn];
bits(VL) operand2 = Z[m];
bits(VL) operand3 = Z[k];

Z[dn] = NOT((operand1 AND operand3) OR (operand2 AND NOT(operand3)));
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