NOTS
Bitwise invert predicate, setting the condition flags.
Bitwise invert each active element of the source predicate, and place the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
This is an alias of EOR, EORS (predicates). This means:
- The encodings in this description are named to match the encodings of EOR, EORS (predicates).
- The description of EOR, EORS (predicates) gives the operational pseudocode for this instruction.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | Pm | 0 | 1 | Pg | 1 | Pn | 0 | Pd | ||||||||||||
Setting the condition flags
is equivalent to
EORS <Pd>.B, <Pg>/Z, <Pn>.B, <Pg>.B
and is the preferred disassembly when Pm == Pg.
Assembler Symbols
| <Pd> |
Is the name of the destination scalable predicate register, encoded in the "Pd" field. |
| <Pg> |
Is the name of the governing scalable predicate register, encoded in the "Pg" field. |
| <Pn> |
Is the name of the first source scalable predicate register, encoded in the "Pn" field. |
Operation
The description of EOR, EORS (predicates) gives the operational pseudocode for this instruction.