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## SMINP

Signed minimum pairwise.

Compute the minimum value of each pair of adjacent signed integer elements within each source vector, and interleave the results from corresponding lanes. The interleaved result values are destructively placed in the first source vector.

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 0 1 0 0 size 0 1 0 1 1 0 1 0 1 Pg Zm Zdn

#### SVE2

SMINP <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

```if !HaveSVE2() then UNDEFINED;
integer esize = 8 << UInt(size);
integer g = UInt(Pg);
integer m = UInt(Zm);
integer dn = UInt(Zdn);```

### Assembler Symbols

 Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.
<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D
 Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 Is the name of the second source scalable vector register, encoded in the "Zm" field.

### Operation

```CheckSVEEnabled();
integer elements = VL DIV esize;
bits(VL) operand1 = Z[dn];
bits(VL) operand2 = Z[m];
bits(VL) result;
integer element1;
integer element2;

for e = 0 to elements-1
if ElemP[mask, e, esize] == '0' then
Elem[result, e, esize] = Elem[operand1, e, esize];
else
if IsEven(e) then
element1 = SInt(Elem[operand1, e + 0, esize]);
element2 = SInt(Elem[operand1, e + 1, esize]);
else
element1 = SInt(Elem[operand2, e - 1, esize]);
element2 = SInt(Elem[operand2, e + 0, esize]);
integer res = Min(element1, element2);
Elem[result, e, esize] = res<esize-1:0>;

Z[dn] = result;```