You copied the Doc URL to your clipboard.

SQRDMLAH (vectors)

Signed saturating rounding doubling multiply-add high to accumulator (unpredicated).

Multiply then double the corresponding signed elements of the first and second source vectors, and destructively add the rounded high half of each result to the corresponding elements of the addend and destination vector. Each destination element is saturated to the N-bit element's signed integer range -2(N-1) to (2(N-1) )-1. This instruction is unpredicated.



SQRDMLAH <Zda>.<T>, <Zn>.<T>, <Zm>.<T>

if !HaveSVE2() then UNDEFINED;
integer esize = 8 << UInt(size);
integer n = UInt(Zn);
integer m = UInt(Zm);
integer da = UInt(Zda);

Assembler Symbols


Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

Is the name of the first source scalable vector register, encoded in the "Zn" field.


Is the name of the second source scalable vector register, encoded in the "Zm" field.


integer elements = VL DIV esize;
bits(VL) operand1 = Z[n];
bits(VL) operand2 = Z[m];
bits(VL) operand3 = Z[da];
bits(VL) result;
integer round_const = 1 << (esize - 1);

for e = 0 to elements-1
    integer element1 = SInt(Elem[operand1, e, esize]);
    integer element2 = SInt(Elem[operand2, e, esize]);
    integer element3 = SInt(Elem[operand3, e, esize]);
    integer res = (element3 << esize) + (2 * element1 * element2);
    Elem[result, e, esize] = SignedSat((res + round_const) >> esize, esize);

Z[da] = result;